Hiroshima Elpida Commences Mass Production of 90 nm DRAM Chips on New 300 mm Wafer Production Line; Newly Expanded E300 Fab Targets 54,000 Wafers per Month, the Largest Semiconductor Capacity in Japan

HIROSHIMA, Japan—(BUSINESS WIRE)—Dec. 1, 2005— Elpida Memory, Inc. (Elpida) and Hiroshima Elpida Memory, Inc. (Hiroshima Elpida) announced today the completion of its new 300 mm production line at its 300 mm wafer fabrication facility (E300 Fab) in Hiroshima, Japan. The monthly 300 mm wafer production volume is expected to reach a capacity of 54,000 by FY Q4, which would make Hiroshima Elpida's E300 Fab the largest semiconductor wafer processing capacity in Japan.

Hiroshima Elpida began construction of a new facility to house the expanded line in June 2004. As scheduled, construction was completed in June 2005, and was followed by the installation of clean rooms and production equipment, as well as several test-runs of factory operations. In FY Q2, the E300 Fab started an average of 30,000 wafers per month. In November 2005, the E300 Fab handled 45,000 wafers per month, and during December 2005, volume is expected to increase to 50,000 wafers per month. Wafer output will likely contribute to shipments starting in 4Q of the current fiscal year ending March 31.

"Our first lot of wafers for mass production of DRAM using advanced 90 nm process technology started on October 17, 2005," said Shuichi Otsuka, president of Hiroshima Elpida. "Our initial ramp has been extremely smooth and successful, and each day we are seeing an increase in the number of wafers processed."

Production yield based on Elpida's 90 nm process technology has been outstanding since the start of mass production, and Elpida intends to have advanced 90 nm process technology account for approximately 70% of total monthly production at the E300 Fab within this fiscal year. Given the synergistic benefits from increased production at E300 and from the migration to 90 nm process, Elpida's shipment volumes during the first half of FY 2006 now have the ability to increase significantly. As a result, Elpida is well-positioned to provide a steady supply of DRAM products to the market in support of greater demand for memory.

For an overview of Elpida Memory's 300 mm wafer line, please see the attachment.

About Elpida Memory, Inc.

Elpida Memory, Inc. is a manufacturer of Dynamic Random Access Memory (DRAM) silicon chips with headquarters based in Tokyo, Japan, and sales and marketing operations located in Japan, North America, Europe and Asia. Elpida's state-of-the-art semiconductor wafer manufacturing facilities are located in Hiroshima, Japan. Elpida offers a broad range of leading-edge DRAM products for high-end servers, mobile phones, digital television sets and digital cameras as well as personal computers. Elpida had sales of 207.0 Yen billion during the fiscal year ending March 31, 2005. For more information, visit www.elpida.com.

The information contained within this news release is current as of the date of release. Please note that the information herein may be revised later without prior notice.


Overview of Hiroshima Elpida Memory 300 mm Wafer Line

Construction site: Hiroshima Elpida Memory, Inc. (on existing company grounds)

Start of construction of expanded line: June 2004

Completion of construction of expanded line (building): June 2005

Start of mass production following line expansion: October 2005

Processing capacity: 45,000 wafers/month (Nov. 2005), 54,000 wafers/month (planned as of FY 2005 4Q)

Company placing construction order: Hiroshima Elpida Memory, Inc.

Designer & builder: Obayashi Corporation

Elpida Memory, Inc. (Japan)
Tomoko Kobayashi, +81-3-3281-1648

Email Contact
Elpida Memory (Europe) GmbH. (Germany)
Peter Westerdorf, 0049 (0)211 23945120

Email Contact
Lee Communications -- PR for Elpida Memory (USA) Inc.
Heather Roberts, 408-288-8681

Email Contact

Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, PA
Senior Formal FAE Location OPEN for EDA Careers at San Jose or Anywhere, CA
Design Verification Engineer for intersil at Morrisville, NC
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, CA
ASIC Hardware Engineer for BAE Systems Intelligence & Security at Arlington, VA
Upcoming Events
DVCon US 2018 at Double Tree Hotel San Jose CA - Feb 26 - 1, 2018
5th EAI International Conference on Big data and Cloud Computing Challenges at Vandalur, Kelambakkam high road chennai Tamil Nadu India - Mar 8 - 9, 2018
DATE '18: Design, Automation and Test in Europe at International Congress Center Dresden Ostra-Ufer 2 Dresden Germany - Mar 19 - 23, 2018
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise