Logic Soft Errors in Sub-65nm Technologies - Design and CAD Challenges - Technical Paper from DAC 2005

Intel

Paper by Subhasish Mitra, Tanay Karnik, Norbert Seifert, and Ming Zhang.

Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) Accurate soft error rate estimation for combinational logic networks; (2) Automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) New cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.


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