Virage Logic Senior Executives Tapped to Deliver Industry Keynotes

CEO and Chief Scientist to Provide Talks on Virage Logic's Vision for Semiconductor Business Models, and Design-for-Yield

FREMONT, Calif., Nov. 29 /PRNewswire-FirstCall/ -- Senior executives from Virage Logic Corporation, a pioneer in Silicon Aware IP(TM) and leading provider of semiconductor intellectual property (IP) platforms (NASDAQ: VIRL), have been invited to share their expertise by giving keynote addresses at two upcoming industry events -- the Executive Forum on Microelectronics and the World Premiere of Cadence Encounter 5.2.

The Executive Forum on Microelectronics, an annual event hosted by the Information Technology Association of Canada (ITAC), has invited Virage Logic's president and CEO, Adam Kablanian, to deliver the conference's plenary keynote address. Kablanian's presentation, "Is the Chipless Model for Everyone?" will examine the economic issues related to a chipless or IP-based business model and its relative attractiveness. He will also participate as a featured panelist at the event.

The 11th Annual Executive Forum on Microelectronics will be held on November 29 and 30, 2005, at the National Arts Centre in Ottawa, Ontario, Canada. For more information, or to register for this event, please go to .

Dr. Yervant Zorian, Virage Logic's vice president and chief scientist, will present the keynote address at the world premiere of Cadence Design's Encounter 5.2. Attendees at this exclusive customer event will hear Dr. Zorian, recognized as one of the industry's foremost experts on chip testability and yield issues, speak on the importance of design-for-yield (DFY) technologies and their critical importance at advanced process nodes in a presentation entitled, "Optimizing SoC Manufacturability." Dr. Zorian's address will highlight a new class of high-yielding IP recently introduced by Virage Logic: Silicon Aware IP(TM). By designing Physical IP (memories, logic and I/Os) with embedded Infrastructure IP for test, diagnostics, repair, and yield enhancements, Silicon Aware IP(TM) enables rapid time-to-volume at advanced process nodes, higher test quality and reliability.

Virage Logic and Cadence Design have previously partnered to enhance low power design and have achieved up to 3.5X reduction in leakage power by building Virage Logic's yield enhancement capabilities directly into Cadence's Encounter solution.

The Cadence Encounter 5.2 event will take place on December 6, 2005, at the AMC Mercado Theater in Santa Clara, CA. For more information or to register for this event, please go to .

About Adam Kablanian

Adam Kablanian co-founded Virage Logic and has served as president, chief executive officer and as a director since January 1996. For more information on Mr. Kablanian, go to .

About Dr. Yervant Zorian, Ph.D.

Dr. Yervant Zorian has served as Virage Logic's vice president and chief scientist since joining the company in 2000. He is also the recipient of the 2005 IEEE Industrial Pioneer Award. For more information on Dr. Zorian, go to .

About the World Premiere of Cadence Encounter 5.2

The world premiere of Encounter 5.2 is a free event and is recommended for Cadence Encounter digital IC design platform audiences only. Customers will get to meet Encounter R&D, get a peek behind the scenes (through in-depth technical presentations), see the latest in digital IC design, and mingle with the who's who of the electronics industry. For more information, or to register for the event, go to OR4960646993 .

About the Executive Forum on Microelectronics

The 11th Annual Executive Forum on Microelectronics, co-hosted by the Information Technology Association of Canada (ITAC) and Cadence Design Systems, will be held on November 29 and 30, 2005, at the National Arts Centre in Ottowa, Ontario, Canada. The event theme is "Creative Destruction: Reinventing the Microelectronics Enterprise." For more information, or to register for this event, please go to

About Virage Logic Corporation

Founded in 1996, Virage Logic Corporation rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Today the company is a global leader in semiconductor IP platforms comprising embedded memories, logic, and I/Os and is pioneering the development of a new class of IP called Silicon Aware IP. Silicon Aware IP tightly integrates Physical IP (memory, logic and I/Os) with the embedded test, diagnostic, and repair capabilities of Infrastructure IP to help ensure manufacturability and optimized yield at the advanced process nodes. Virage Logic's highly differentiated product portfolio provides higher performance, lower power, higher density and optimal yield to foundries, integrated device manufacturers (IDMs) and fabless customers who develop products for the consumer, communications and networking, hand-held and portable, and computer and graphics markets. The company uses its FirstPass-Silicon(TM) Characterization Lab for certain products to help ensure high quality, reliable IP across a wide range of foundries and process technologies. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide. For more information, visit

Safe Harbor Statement under the Private Securities Litigation Reform Act of 1995: Statements made in this news release, other than statements of historical fact, are forward-looking statements, including, for example, statements relating to operational issues, trends, business outlook, products, and customer relationships. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic's ability to improve its operations; its ability to forecast its business, including its revenue, income and order flow outlook; Virage Logic's ability to execute on its strategy to become a provider of semiconductor IP platforms; Virage Logic's ability to continue to develop new products and maintain and develop new relationships with third-party foundries and integrated device manufacturers; adoption of Virage Logic's technologies by semiconductor companies and increases or fluctuations in the demand for their products; the company's ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies; the company's ability to obtain royalty revenues from customers in addition to license fees, to receive accurate information necessary for calculating royalty revenues and to collect royalty revenues from customers; business and economic conditions generally and in the semiconductor industry in particular; competition in the market for semiconductor IP platforms; and other risks including those described in the company's Annual Report on Form 10-K for the period ended September 30, 2004, and in Virage Logic's other periodic reports filed with the SEC, all of which are available from Virage Logic's website ( or from the SEC's website (, and in news releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.

NOTE: All trademarks and copyrights are property of their respective owners and are protected therein.

CONTACT: Sabina Burns, Virage Logic Corporation, +1-510-743-8115, or
Email Contact; or Kerry McClenahan of McClenahan Bruer
Communications, +1-503-546-1002, or Email Contact, for Virage Logic

Web site:

Review Article Be the first to review this article

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
2017 IoT Developers Conference at Santa Clara Convention Center California - Apr 26 - 27, 2017
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy