The Case of the Missing Via: Sequence Design
Any other topic that my readers might be interested?
Feature size. These power problems become exacerbated as we go forward with technology. There's a couple of reason for it. One is naturally the line width becomes smaller. Not only does it become narrower but it also tends to become thinner because there is vertical scaling going on. That means the resistance of these routes goes up. That's just going to make it harder for power grid designers. Secondly, leakage current is going through the roof literally. I mentioned briefly about the gate leakage at 90nm and 65 nm. That's just one of the components. There are several other leakage components growing dramatically. What we are seeing is that it is becoming very difficult to pull out one single perspective or one parameter and fix that one alone. For example, decoupling capacitors. You can use these gate oxides capacitor but they are going to leak like crazy. They will leak even more as you go to smaller line widths. You can avoid that by using metal-to-metal decoupling capacitors but they are not as effective and you need better automation in terms of placement and sizing. That affects potentially your initial placement and how well you can close timing. What we are seeing as the line widths decrease is the whole design process is becoming more complicated. There's no news there. We've all known that. What is eye opening for some people is the extent to which the various power issues are becoming intimately intertwined with all the other issues. That's where we play, which is really the confluence of power, timing and signal integrity. CoolCheck is a new capability in that regard. CoolTime voltage drop optimization really draws in our strength in power, timing and SI, rolls them all together to come up with something that other people just can't do.
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