The Case of the Missing Via: Sequence Design

What is the packaging and pricing of CoolCheck?
$80,000 for a one year license. Typically logged into a license server, conventional LM license.

Product availability?
It's in beta test right now. It will come out shortly with 2005.3 release due later this month.

How many beta sites?
Three active beta sites, several more in line to use it.

Any customer willing to go on the record?
There is one cited in the announcement.

At risk of asking the obvious, why is power an issue and why a growing issue?
We see as a company a set of power problems in two broad categories, one that we call power grid integrity and one that we call power management. In the later category it is all about reducing power. Most all of us have come face-to-face with this with our cell phones, laptops or PDAs. We want our batteries to last longer. We also run into this with tethered machines where they are generating too much heat. One of the big techniques that designers have used is to lower the voltage. What we've seen for several years now is tat the supply voltage has been dropping. A number of years ago it was 5 volts then 3.5 volts and so forth. Now we have a lot of designs at 1 volt, some a little above and some a little below. When the voltage drops that low, the integrity of the power grid becomes a big concern. That leads us to the second class of problems we see namely integrity problems. Power grid integrity has always been an issue but now has become highly exacerbated. If you look, for example at the big high performance microprocessors from Intel, you can have 100 amps running around these things. 100 watts on a 1 volt power supply, that's 100 amps. That's not even peak current. Because the current can be so large is one reason why you have to these grids. The second reason is that when the supply voltage drops so low, your noise margins become very small indeed. It requires careful design, careful verification to show that the chip is manufacturable, that it's going to work across a variety of operating conditions. These situations have caused the IC design industry, the EDA industry to pay a lot of attention to how power is calculated, what its effects are on certain circuit parameters and in particular to what happens on the power grid and how that affects the rest of the chip. With this attention designers need tools, techniques and methodologies. The first was really static IR drop which is doing V = IR for all points on the power grid where I is an average current. I think most everyone has known for a long time that this is an approximation, a fairly rough one but that was the best we had for quite a while. Then we and our competitors came along with dynamic voltage drop. This catches more problems than static does because we are using dynamic waveforms for the current. For example using static IR drop (V=IR), you can't tell what the effect of packaging does on the voltage waveforms on your power grid. Again if you are doing just V=IR calculation, you can't tell what the effectiveness of decoupling capacitors will be on the power grid. The dynamic voltage drop analysis techniques have been developed to look at the power grid issues in much more detail and to enable more sophisticated design and mitigation techniques. With CoolCheck we are talking about a different look at this all together. We are not trying to say that there is something wrong with dynamic voltage drop analysis but its being time based or vector driven, whatever you want to call it. By definition you can't check all the connections. So we have come up with an adjunct capability with CoolCheck that will check all the connections in the power grid resistance space. We're trying to arm the designers and verification engineers with a variety of tools to try to check the various issues that they are concerned with. A few years ago there were only a couple of power issues that people were concerned with. Now there are all sorts of power issues that people are concerned with. We're trying to help all these guys with various perspectives they are focused on.

What are the typical solutions to the problems other than those that CoolCheck finds? Add decoupling capacitors, create voltage islands ..?
There are several different approaches. I would say that the most time honored one is to make the grid bigger and fatter. Generally most teams in the past have taken the approach that we are so concerned about these issues and we really don't know how to analyze them, we were just going to be way over conservative about these issues and design this big honkering power grid so that we don't have to worry about it. As time has gone on they began to realize that's problematic because that can take up too many wiring resources. They are trying to scale that back but in doing so they have begun to worry about just how much voltage drop they have. So when they find a spot where there is too much voltage drop they typically go in and maybe size up locally as opposed to doing it all over the place, add an additional strap in certain spots, sort of an ad hoc approach. That will work in the IR drop domain. That really attacks R. If they have problems due to what we have called circuitous route or missing vias, if they find those they will go fix them with specific techniques. If it is missing a via, that's pretty straightforward. You simply go and add the via. The hard part is finding it. If it is a circuitous path, maybe they will change the placement a little bit, they will add some additional power straps. Once the static IR drop has been verified to be reasonable, then they will begin looking at dynamic effects. Here there are a couple of techniques. The chosen technique depends upon which issue they have. If the issue is broad based, dynamic peaks are too large, they will look to see if it's an inductance problem. If it's a package inductance problem, i.e. the L of the package interacting with the di/dt of the circuit, if that is causing the problem they will probably try to use a better package that will have less packaging inductance. That tends to be fairly expensive. These packages with better electrical characteristics can be fairly costly. If they can't really bare that cost or the dynamic voltage drop effect is more local, they will look to utilizing decoupling capacitors. In this case capacitors will be added between the power supply and the ground to basically serve as local charge reservoirs, to smooth out the current peaks. Until recently a number of company design teams would do what we call blind decap insertion where in a pseudo prophylactic manner put decaps wherever they had open space, filler cells or space that wasn't utilized under the assumption that more decoupling capacitors can't hurt and can only help.

What is now occurring due to some of our voltage drop optimization technology we recently introduced is that we can put decoupling capacitors exactly where they are needed so that we don't put too many. We don't want to put too many. There are a number of reasons. One is power and one is manufacturability. Most decoupling capacitors are built using gate oxide, basically transistors which are tied off so we are using the capacitance between the body and the gate. Beginning around 90 nm to 65 nm these capacitors leak, so called gate leakage. The more these thin gate oxide capacitors are used. If you are in a power sensitive application, it behooves you to use the smallest number you need. The second issue there is that gate oxide are defect sensitive. You don't want to have any defects in these areas. The more of these you use, the more likely you are to have yield issues, manufacturability concerns. Designers today are certainly using decoupling capacitors but they are trying to do it in a much smarter way, to use the smallest number possible and to place them exactly where they are needed. That's part of our technology offering.

« Previous Page 1 | 2 | 3 | 4 | 5  Next Page »


Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
Currently No Featured Jobs
Upcoming Events
CDNLive Japan 2018 at The Yokohama Bay Hotel Tokyu Yokohama Japan - Jul 20, 2018
MAPPS 2018 Summer Conference at The Belmond Charleston Place Charleston SC - Jul 22 - 25, 2018
International Test Conference India 2018 at Bangalore India - Jul 22 - 24, 2018
SRTC-2018 at The Leela Ambience Gurugram NEW DELHI India - Jul 25 - 26, 2018
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise