Improv's Jazz DSP Processor is a configurable VLIW processor that incorporates many advanced architectural features including parallel datapaths, a distributed register system, code compression, and power management. It is supported by a flexible design methodology used to customize the computational resources and instruction set of the processor, while supporting a comprehensive tool chain.
Improv's Jazz DSP processor model and debugger will be integrated into MaxSim for easy deployment and combination with leading micro-controller (MCU) cores. Improv will use MaxSim to produce virtual prototyping boards that its licensees can use for evaluation and as software implementation platform. MaxSim's ultra-fast simulation engine enables simulation speeds in excess of 100kHz for cycle-accurate models and more than 1MHz for functional models, providing ample speed for effective embedded software development.
iRoC Technologies announced SERTEST, a new bundle of professional services for Soft Error Rate (SER) simulation, radiation testing and technology characterization of all VDSM ICs. SERTEST enables semiconductor manufacturers, system houses, fabless companies and IP providers to qualify their product with respect to an acceptable SER to assure the highest system reliability, availability and security.
SERTEST increases flexibility and reduces test engineering steps and simulation calculations while providing an accurate SER of CMOS chips and is easily customized to accept a broad range of different semiconductor devices as well as any technology process. Currently SER evaluation and qualification is a bottleneck due to both simulation and radiation tests because of tester stringent constraints set by beam facilities. iRoC provides a specific probe IP associated with a SEU simulator to speed-up simulation and an innovative programmable-based tester to avoid crippling PCB development for cosmic rays tests. SERTEST features the capability to merge SER evaluation and qualification into reliability test procedures without increasing the critical path length.
Real Intent has added formal Clock Intent verification to its electronic design verification system, Verix. Assertion-based formal Clock Intent verification analyzes and verifies the stability and correctness of data transfer between clock domains. It automatically identifies the clock domains and the hazards for signals crossing those domains and advises the designer about appropriate assertions to formally verify the data transfer.
The Verix Clock Intent verifier looks at the RTL design description and automatically identifies the clock domains within the design and the signals crossing the clock domains, as well as identifies the absence or presence of synchronizers at the clock domain boundaries, and determines Verix assertions that can exhaustively verify the data transfer stability across the clock domain boundaries.
Model Technology, a Mentor Graphics company, said that its leading mixed-language hardware description language (HDL) simulation tool, ModelSim, has been qualified for Verilog support from Fujitsu Electronics Device Group for all current and future released ASIC series. This extension enables customers to use their design language of choice, Verilog or VHDL, while remaining in the ModelSim environment, which significantly decreases their turn-around time.
ARM, Synopsys, Inc., and Taiwan Semiconductor Manufacturing Company, Ltd. have collaborated in generating a proven, fast track system-on-chip (SoC) integration methodology for use by ARM Partners who use TSMC as a foundry. The companies have linked the TSMC Reference Flow and the ARM-Synopsys Reference Methodology to create an easy-to-use SoC Integration Methodology Guide that reduces risk and accelerates time-to-volume. This is the first in a series of initiatives between the three companies intended to provide their mutual customers with access to the latest silicon processes and advanced methodologies.
With the SoC Integration Methodology Guide, both customer-owned tooling (COT) and integrated device manufacturer (IDM) designers could take advantage of the combined benefits of the TSMC Reference Flow and the ARM-Synopsys Reference Methodology. The TSMC Reference Flow provides developers with a silicon-proven methodology that dramatically reduces time-to-volume by enabling direct manufacturability to TSMC' industry-leading process technologies. The ARM-Synopsys Reference Methodology enables SoC developers to access ARM microprocessor cores quickly and efficiently.
TSMC is supporting the SoC Integration Methodology today for designs incorporating ARM hardened microprocessor cores. The SoC Integration Methodology has support for the following Synopsys tools: Synopsys' Physical Compiler, Chip Architect, Design Compiler, DC Ultra, DesignWare, Formality, Power Compiler, DFT Compiler, TetraMAX ATPG, PrimeTime and VCS. The SoC Integration Methodology is modular and based on standard interfaces allowing for the integration of complementary tools, libraries and IP cores. The TSMC SoC Integration Methodology Guide is now available and can be accessed at: http://www.online.tsmc.com.
EDAptive Computing, Inc. said it would unveil its EDASTAR methodology for design of large, complex mixed-technology systems, at next week's Design Automation Conference in New Orleans. The company said its EDASTAR methodology leverages pre-existing design requirements to create unambiguous specifications that can be systematically analyzed to avoid downstream design errors and significantly shorten verification times. EDASTAR addresses the compelling need to shorten design cycles, and reduce design errors and verification costs.
IMEC said it is in discussions with Cayman Islands-based Semiconductor Manufacturing International Corporation (SMIC) based in Shanghai, China, to explore a long-term partnership for the development of advanced semiconductor process technology. IMEC's support would consist of consulting services and training towards SMIC's own in-house development of advanced CMOS technology. The contract discussions between both organizations began mid April, with the signature of a Letter of Intent. In order to prepare the next step, IMEC initiated the procedure of applying for an export license with the Belgian authorities, at the beginning of May.
Siroyan opened a new facility in San Jose, California, which will initially support the company's U.S.-specific sales and marketing team, as well as a customer-focused applications group. Over the next two years, the company said it plans to further expand its US presence by opening new sales facilities and design centers to best service the growing market for its scalable DSP soft-core technology.
Silicon Metrics reported that 1st Silicon, Malaysia's first commercial integrated circuit wafers foundry, has standardized on SiliconSmart CR to meet their demand for accurate characterization of standard cell timing and power models. 1st Silicon said its goal is to establish a world-class manufacturing operation and to operate its manufacturing facilities as if it is the customer's own foundry. To help meet that goal, 1st Silicon said SiliconSmart CR's rapid throughput and accurate characterization capabilities will allow it to perform the task of matching design libraries with its manufacturing processes on an ongoing basis.
Avant! Corp. introduced Distributed Routing for its Astro advanced physical optimization, placement and routing system. Recently, on a complex video processor design, iS3 reportedly achieved a 3.5X speedup on four processors compared to single-processor routing. Scalable routing performance, which can exceed 6X speed improvement with 8-node distributed processing is achieved by Astro Distributed Routing, the company claims. claims.
Avant! also reported that Nordic VLSI ASA, a leading independent European IC design house that develops, produces, and delivers state-of-the-art integrated circuits, has successfully taped out a high-performance IC for digital sensor applications using the Astro physical design-closure capability, part of Avant!'s SinglePass-SoC tool set. Nordic VLSI said it achieved timing closure with signal integrity in half the time normally required by its previous design flow.
Also from Avant!: BAE SYSTEMS Information & Electronic Warfare Systems (IEWS) a leader in radiation-hardened IC design for military and aerospace applications, has selected Avant!'s Cosmos custom-IC design environment and the SinglePass-SoC solution for their IC design needs.
SandCraft, Inc. has chosen the DynaCore solution from Circuit Semantics, Inc. for deep submicron block characterization and static timing analysis. SandCraft said it chose DynaCore because it is the best alternative on the market today for characterization and static timing analysis, and the only one that supports both custom and ASIC designs. SandCraft has used DynaCore as part of their final sign-off timing flow for several successful tape outs.
Synplicity, Inc. announced Faraday Technology Corp. now supports Synplicity's Synplify ASIC synthesis software in its ASIC design tool kit. Libraries for the Synplify ASIC software are accessible on Faraday's Web site at http://www.faraday.com.tw. With this announcement, Synplicity now offers its customers ASIC vendor support in Asia, Europe, Japan and North America.
AXYS Design Automation, Inc. expanded its management team with the appointment of Frank Schirrmeister as vice president of business development. Schirrmeister joins AXYS Design from Cadence Design Systems, Inc. where he was business director in the Systems and Functional Verification Business Unit.