According to Cadence, the complaint is based in part on a ruling in June 2000 by the United States District Court for the Northern District of California which dismissed a patent infringement lawsuit filed against Quickturn by Meta, Mentor and Aptix. The dismissal was based on a set of findings that Aptix and its CEO had engaged in a shameful pattern of fraud, including the creation and attempted concealment of fabricated evidence, intended to deceive Quickturn and the District Court. The U.S. Court of Appeals affirmed the District Court's June 2000 ruling in November 2001.
In prepared remarks, Penny Herscher, Cadence executive vice president and chief marketing officer said that the court rulings, “support our long-standing contention that Aptix, with the active support of Mentor and Meta, engaged in outright fraud in the patent infringement complaint against Quickturn. This fraud is the basis for our current complaint. With this lawsuit we are serving notice -- we will not tolerate this sort of malicious prosecution or attempts by competitors to unlawfully abuse the legal system to distract us from our priority, the delivery of leading-edge technologies and second-to-none customer service and support.”
Further, “The facts of the case are clear -- the defendants named in our complaint conspired to fabricate evidence and claim intellectual property that is rightfully ours. We cannot allow this type of fraudulent activity to go unchallenged. We will protect our intellectual property, and we look forward to prevailing in court.”
Expectedly, Mentor president Gregory K. Hinckley said in response to the suit, that while the company had not yet received a copy of the complaint, they believe the claims against Mentor are old news, dating prior to June 2000, and have been twice rejected by the courts.
Also, he said that they are, “disappointed that Cadence would choose to disparage us by re-asserting previously rejected claims. Judge William Alsup of the Northern District Court of California (Docket # C98-00762 WHR (EDL)) ruled in June 2000 that there was no evidence of any Mentor wrongdoing. This ruling was then upheld on appeal in 2001. We would expect that based on these existing rulings this case shall be dismissed,” Hinckley said.
In other legal wrangling, Mentor reported that it won a third summary judgment of patent infringement, the latest for its patent #5,754,827, against Cadence's Quickturn Mercury and Mercury-Plus product lines.
The Court also rejected a motion of patent invalidity by Cadence on this patent. These rulings come in Mentor's patent infringement and theft of trade secrets case against Cadence, which is scheduled for trial on January 6, 2003.
Dynalith's new PCI card product, iPROVE enables FPGA users and IP designers to verify their designs in a much more efficient and versatile way than conventional FPGA-based verification schemes, the company reported. iPROVE uses 66MHz/64bit DMA-enabled PCI interfacing for higher hardware performance and provides C-interface and HDL-interfacing in the form of API for testing and HW/SW co-simulation. The product also has a Built-In Logic Analyzer and Data Pumping Port to monitor various signals and to send and receive data through external connections, respectively. iPROVE supports SystemC, SCE-MI and TestBuilder. For floating-point multiplier and IDCT cases, iPROVE provides software simulation that is 1000 to2000 times faster than pure software simulation, the company asserted. Dynalith's partnership with Xilinx, Inc. allows the product to support Xilinx devices up to the Virtex II XC2V6000 and will support the Xilinx Virtex II Pro family soon, Dynalith reported.
Also from Xilinx, the company is giving early access of a new technology designed for both hardware and software engineers involved in the common design of programmable systems using Xilinx FPGAs with MicroBlaze and PowerPC processor cores. The new technology expands the company's current solution for programmable systems by enabling customers to define an entire system in ANSI-C to obtain the most optimal implementation by rapidly partitioning and repartitioning between hardware and software, Xilinx said.
In related news, Xilinx also announced its Embedded Development Kit – a design environment for embedded system development using Xilinx embedded processors, which also provide foundational technology for its new co-design capability.
The technology provides a complete set of tools for designing, debugging and optimizing complex systems that use resources such as processors, RAM, DSP functions, high-speed I/O technology, and high density FPGA logic. The co-design tools are unique in the system design tool world with a library of hardware and software components, called Processing Elements (PE) optimized for particular functions. This capability enables the customer to use a best-in-class and domain-specific tool to create an optimized PE. A re-partition is a compile time switch, which enables one to profile, convert to a hardware/software implementation and debug in a matter of minutes rather than days or weeks. The hardware and software PEs come from a variety of sources, including Xilinx and third-party AllianceEDA, AllianceCORE, and Embedded Tools partners.
The announced co-design technology enables a true software-centric design paradigm as the technology re-uses proven hardware implementations in an ANSI-C based design flow. This opens up the capability of using the whole processing potential of the FPGA with embedded processor cores to the software design community.
SynTest Technologies, Inc. announced that its TurboFault fault simulator now has a link to the market-leading Debussy Knowledge-based Debug System from Novas Software, Inc.
Altium Limited announced P-CAD 2002, a new version of its P-CAD PCB design system for layout specialists, contains has over sixty new and enhanced features. Interface elements were redesigned in P-CAD 2002 to give PCB layout specialists enhanced ease of use and a more productive design environment, the company explained. New to the tool is the Design Manager feature that allows users to view and manage design data more easily. It presents spreadsheet-like component and net views that are integrated into the PCB layout environment, allowing superior control over key elements of the design. Another new feature is the Visual Placement Area interactive rules-based placement tool that, when a component is being placed, analyses design constraints and displays overlays representing the legal regions of the board in which a component may be placed. This feature makes the critical component placement phase of PCB design faster and gives more control to the designer.
P-CAD 2002 also allows for the trace of an individual net, connections and objects in their own unique colors so designers can easily see individual nets in the context of the board.
Other new features of P-CAD 2002 include support for Valor's ODB++ file format, support for True Type fonts in Gerber and ODB++, component clearance rule checking, and a number of usability-targeted GUI refinements.
Sequence Design appointed Alan Lipinski to senior vice president of worldwide field operations, responsible for sales and application engineering for the company's growing roster of customers. He will report directly to Sequence president and CEO, Vic Kulkarni.
Before joining Sequence, Lipinski was director of Silicon Valley sales for Cadence Design Systems, managing major accounts such as Philips, Broadcom, and Nortel. In a 25-year career, he has held a number of senior sales, marketing, and executive posts, including CEO of a venture-capital firm. Direct EDA, computer, and semiconductor experience includes time with Virtual Silicon, Exemplar, Meta Software, Dazix, Computervision, Fairchild, and Gen Rad. He has led efforts to build international sales and support organizations while significantly growing business. At Meta, where he served as vice president of worldwide sales and marketing, Lipinski boosted sales to $35 million before the company's successful IPO in 1995. Lipinski received his bachelor's degree in electrical engineering from Southern Illinois University.
Nassda Corporation announced that Innovative Systems & Technology Corporation (Insyte) is using Nassda's HSIM hierarchical full-chip simulator and analysis tool for verification of SoC integration, custom memories and analog circuits in CMOS and BiCMOS technologies.
Insyte said it purchased multiple HSIM licenses the tool demonstrated superior accuracy and solved performance problems of other tools. Insyte also said it has integrated HSIM into its full-custom design flow, and its engineers now use HSIM for verification of customized embedded SRAMs and analog circuits. HSIM also anchors Insyte's SoC verification flow, where it provides a significant advantage for integration of IP cores in SoC designs, according to the company.