Accellera Workshop Showcases SystemVerilog 3.0

Mentor Graphics Corp. announced co-verification model support for the ARCtangent user-customizable RISC/DSP core from ARC International, a provider of configurable SoC platform technologies. Comprehensive development platforms may include pre-verified peripherals, system software, embedded middleware and tools. The ARCtangent microprocessor is a user-customizable RISC/DSP core that allows developers to modify and extend the architecture for specific applications. Mentor Graphic's Seamless verification tool will help designers of ARCtangent microprocessor-based systems to model the customized interactions between components in a virtual environment and reduce resource allocations for physical prototyping.

Monterey Design Systems announced the latest release of the company's tool set: IC Wizard hierarchical design planner, Sonar physical synthesis and prototyping tool, and Dolphin physical implementation system. Release 2.5 of the Monterey tool set is the fastest, highest capacity, and most functionally complete product line offered to date by the company. Recently announced tape-outs and target designs include consumer electronics chips, streaming data processors, and switch fabrics ranging in size from one million to 20 million gates on process technologies of .15 micron, .13 micron, and 90 nanometers.

Prior releases of IC Wizard were optimized to deal with hundreds of hard blocks, but worked best when standard cells were clustered into blocks at the top level. IC Wizard 2.5 support un-clustered standard cells at the top level and automatically configures the timing and physical constraints taking into consideration all instantiations of the block within the context of the chip-level design plan. Sonar and Dolphin 2.5 offer improvements in circuit performance of 10%-15% by incorporating new physical synthesis and placement algorithms. Memory utilization has been improved to handle designs twice as large as prior versions increasing the flat capacity beyond 5 million gates. When combined with the hierarchical capabilities in IC Wizard, capacity scales upwards of 100 million gates.

Nassda Corp. announced that National Semiconductor has adopted Nassda's HSIM hierarchical full-chip simulator and analysis tool for the design and verification of complex ICs. Under a multi-year agreement, National is deploying HSIM licenses worldwide and standardizing on the simulator. HSIM provides detailed circuit-level analysis of timing and power behavior and signal integrity effects, analyzing circuit behavior while taking into account the electrical and parasitic effects of nanometer-scale silicon.

Novas Software, Inc. announced that Sanyo Semiconductor Co. (SSC) has adopted the Novas Debussy Knowledge-Based Debug System as its standard IC debug system. SCC is the one of the Sanyo group companies involved in developing system LSIs with microcomputers and system LSIs for digital consumer devices. SCC signed a multi-year purchase agreement with Novas for broad deployment of Debussy within the LSI System Division, enhancing product development with more functionality, higher quality, and greater reliability for digital cameras and digital TVs. The Debussy debug system automates the tracing, visualization, and analysis of causes and effects in Verilog, VHDL and mixed-language descriptions.

Oridus, Inc. announced a licensing agreement with Cadence Design Systems, Inc. Under the terms of the agreement, Oridus will equip Cadence field application engineers and customer support centers with its SpaceCruiser client/server software for real-time desktop sharing and web conferencing. Oridus' cross-platform and cross-network products utilize the Internet and corporate intranets and allow customers to control software and capabilities deployed into their network environment. The products employ several levels of security including 128-bit SSL encryption, LDAP integration, and role-based authentication procedures.

Additionally, Oridus and UMC announced that UMC has expanded its on-line customer services with Oridus' web-based mask data MEBES (Manufacturing Electronic Beam Exposure System 2) reader tool, MebesCruiser. UMC customers can view and browse their MEBES database of an IC, or link teams of engineers for collaboration via web conferencing in a highly secure, on-line mask data environment. MebesCruiser, when integrated into UMC's web environment, displays a multi-gigabyte mask file onto desktop PCs or workstations running Windows, UNIX, or Linux operating systems.

SiRF Technology, Inc. and Motorola, Inc.'s Semiconductor Products Sector (SPS), announced an agreement to integrate SiRFstarII Global Positioning System (GPS) cores with Motorola wireless baseband and applications processors. Motorola plans to incorporate SiRF's GPS technology into a line of location-aware wireless baseband and applications processor chipsets. The chipsets will utilize SiRF's SiRFstarII GPS baseband and RF IC core technology. Motorola intends to implement an enhanced version of SiRF's RF IC technology using the Silicon Germanium-Carbon module of its advanced RF BiCMOS wafer process.

Verisity Ltd. and Novas Software, Inc. announced that Novas has joined Verisity's LicenseE program. As a member of the program, Novas will implement support for Verisity's e verification language in its debug systems, as well as participate in the e language standardization efforts. Verisity also announced that it will join Novas' Harmony program to promote verification methodologies and tool interoperability. By joining the LicenseE program, Novas will build on existing data transfer integration between Specman Elite and the Debussy Knowledge-Based Debug System. Verisity's LicenseE program was created to facilitate verification tool interoperability and standardization. Program members receive open access to the e language, including a stand-alone e parser, and participate in the e Steering Committee.

Xilinx, Inc. and Tarari, Inc. announced that Tarari has selected Xilinx reprogrammable chip technology in the development of the Tarari Content Processing Platform. Tarari content processors are hardware and software-based subsystem building blocks that snap into servers, appliances and network devices, and allow for the inspection of application layer content at network speeds. Tarari and Xilinx plan to continue to work together in the development of next generation products for the application-layer content-processing markets.

Coming soon to a theater near you

IEEE International Electron Devices Meeting - December 8th to the 11th, San Francisco and the Hilton Hotel will plays host to IEDM, the premier scientific meeting covering advances in electron devices. Annually a showcase for future trends in transistor physics and material science, the leading lights from academia and industry will present their latest R&D. The plenary talks on Monday feature presentations on “Lithography for Sub-100nm Applications,” “Chip Technologies for Entertainment Robots: Present and Future,” and “Photonic Bandgap Based Designs for Photonic Integrated Circuits.” The keynote speaker at Tuesday's lunch will be Intel's Dr. Andrew Grove discussing: “Changing Vectors of Moore's Law.” Proving that even engineers can party hardy, the ever-popular Tuesday evening wine-and-cheese panel sessions will offer attendees a choice: “Embedded Memories for SoC - What Makes Sense, Cents?” or “Will SOI Ever Become a Mainstream Technology?” See for registration information.

Electronic Design and Solution Fair 2003 - The 3rd annual conference is taking place in Yokohama, Japan on January 30th and 31st and will run concurrently with the FPGA/PLD Design Conference and the University Plaza exhibition. EDSFair aims to provide technology interchange between industry, academia, and government organizations and will focus on SoC product development. Organizers report that EDSFair was developed as a platform for publicizing the newest developments combining leading-edge EDA technologies, devices, and IP design services. In 2002, EDSFair established a cooperative relationship with EDAC and was viewed as one of the largest comprehensive exhibitions in Asia. Details are available at

International Conferences on VLSI and Embedded Systems Design - 2003 will be the first year in which the 16th International Conference on VLSI Design and the 2nd International Conference on Embedded Systems Design will be held jointly. The conference will take place next month in New Delhi, India, from January 4th to 8th and is being sponsored by the VLSI Society of India, the Ministry of Information & Communications Technology for the Government of India, IEEE, ACM, and NASSCOM. The theme of the conferences is “Design Convergence in SoC Design.” Business leaders and designers from all over India - and outside of India - participate in the conference. The program will include two full-day tutorials, technical paper sessions, panel discussions, and an exhibition. Advance program and registration information is available on the conference website at

OEA International, Inc. is sponsoring a free technical seminar on December 12 <

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