Accellera Workshop Showcases SystemVerilog 3.0

A truce is called in the system-level language wars

The foot soldiers in the system-level language wars appear to have climbed out of the trenches and traded in their battle fatigues for suits and ties. Looking and sounding for all the world like distinguished diplomats negotiating a peace accord, representatives from two of the previously warring factions - SystemVerilog and SystemC - shared a stage in front of a sold-out crowd in Santa Clara, CA on November 5th and spoke enthusiastically about mutual cooperation and respect for their various technology initiatives.

The day-long Accellera workshop sponsored by Synopsys, Mentor Graphics, and Real Intent - “Accellera's Verilog Evolution: An Introduction to SystemVerilog” - heard both sides pledge to move forward on behalf of beleaguered chip designers, to provide integrated language options for everything from system specification to gate-level layout and design verification. This level of bonhomie would have been unthinkable a few short years ago, but the perseverance of the hard-working committees at Accellera seems to have paid off - aided, undoubtedly, in no small measure by the Synopsys acquisition of Co-Design earlier this year.

Accellera - itself a peace initiative created in 2000 out of two previous standards bodies, VHDL International and Verilog International - was chartered to find a common ground between the two HDL constituencies. Meanwhile, Co-Design, home to Verilog author, Phil Moorby, was the spring board for the Verilog-turned-system-spec-language, Superlog.

Subsequently, Accellera benefited from Co-Design's donation of the synthesizable portion of Superlog, Verplex's donation of assertion libraries, and Real Intent's and Co-Design's donations of assertion syntax and semantics and the move was on to create SystemVerilog - an extension of the IEEE 1364 Verilog-2001 standard - and take the HDL to a higher level of existence as a system specification language meeting designers' demands in the emerging era of system-on-a-chip (SoC).

However, not everyone agreed that system specifications could be articulated by limited HDL constructs. Critics believed that higher level languages had to be the source of an over-arching language for system specification, hardware design, and verification. From various corners in the industry, C-based system languages sprang up and gathered momentum - System C, in particular, benefiting from high-profile encouragement from Synopsys and other EDA players.

It was of no small import that the software guys wanted to see things progress in the C direction - a language they were raised on - while the hardware guys were equally determined to see their beloved HDLs win the day. As it turns out, the truce in the language wars - at least between SystemC and SystemVerilog - currently succeeds in moderately satisfying both sides. SystemVerilog 3.0 has been beefed up with a host of assertion constructs to meet verification demands while SystemC has been legitimized as a robust solution for system-level specifications. Accellera and Synopsys are commending both languages.

Following a keynote address by Mentor Graphics' Dennis Brophy, Stu Sutherland of Sutherland HDL, Inc. presented a detailed tutorial on SystemVerilog 3.0. Then Steve Meier of Synopsys and Rajeev Ranjan of Real Intent expanded on Sutherland's tutorial with discussions of the assertion-based verification and formal verification components of SystemVerilog.

Sutherland said the 3.0 release offers capabilities that exceed previous releases by orders of magnitude. He emphasized that Accellera is attempting to move at a faster pace than the infamously slow IEEE committees to establish and document the SystemVerilog 3.0 standard. He said working specs should be made available and put to good use earlier than traditional IEEE practices allow for. As such, Accellera hopes to have full documentation and code for SystemVerilog 3.0 ready by Q2 2003 in time for DAC. Asked what happens to the SystemC initiative with the introduction of SV 3.0, Sutherland said, “SystemVerilog won't replace SystemC. SystemVerilog will make it possible for software people to work in SystemC and hardware designers to work in Verlog. It will allow the integrations of both of their effots.”

If ever there was an enthusiastic evangelist for Superlog - and SystemVerilog - that would have been Co-Design's Dave Kelf , now Senior Director of Marketing, Verification Technology Group, at Synopsys. Dave's contagious optimism today is directed at the new language cohesion in the industry: He says there's been a “bit of a re-org” within Synopsys and the SystemVerilog people and the SystemC people are now working side-by-side. “It's great,” he says. If Dave Kelf sees the move to promote both languages as a positive one, who dares argue?

Industry News

Agere Systems Inc. introduced the FlexPHY IC, a new single-chip physical layer (PHY) transceiver that reduces space and power by 50+ percent over existing two-chip solutions, and enables high transmission signal quality for multi-service metropolitan edge-to-core networks. A PHY transceiver chip transmits and receives data between the physical (optical fiber) and information processing layers. On a network line card, Agere's FlexPHY chip resides at the boundary between the protocol framer and the optics. The FlexPHY device addresses jitter margins, power consumption and integration for system vendors targeting 10-gigabit SONET/SDH, Ethernet, and Fibre Channel networks. Samples of the FlexPHY chip are expected to be available in Q1 of 2003, with volume production expected by Q2. The market for 10-gigabit PHYs is expected to increase from $276 million in sales in 2003 to $780 million in 2006.

Aldec, Inc. announced that designers who use Xilinx Foundation legacy schematics in their designs can port them directly into Aldec's Active-HDL's high-performance, mixed-language simulator to be implemented in any Xilinx device. The ported schematics are translated into HDL block diagrams and are graphically represented as native schematics files that previously existed in Foundation. Designers can use the pre-existing schematic modules instead of having to re-create the designs in HDL code. By supporting both schematics and HDL modules in a single environment, Active-HDL allows designers to re-use legacy designs in support of new Xilinx devices. Aldec initially authored and developed all design editors and project managers for the Xilinx Foundation Series software.

ARM announced that more than 25 partners have signed up to provide support and technical contributions towards the development of the next generation of the AMBA (Advanced Microprocessor Bus Architecture) specification. AMBA is an open standard, on-chip bus specification freely available from ARM that details a strategy for the interconnection and management of functional blocks that make up an SoC. AMBA 3.0 technology will be available for public release in Q1 of 2003.

Twenty-five companies have collaborated on the development of the AMBA 3.0 standard, including: Agere Systems, Agilent, Atmel, Cadence Design Systems, Inc., Conexant Systems, CoWare Inc., Infineon, LSI Logic, Mentor Graphics, Micronas, Motorola, NEC Electronics Corp., NEC Electronics (Europe), Philips Semiconductors, Samsung, STMicroelectronics, Synopsys, Toshiba Corp., and Verisity.

Rafi Kedem, Senior Director of the Processor Cores Technology Group at LSI Logic said, “AMBA 3.0 technology introduces new capabilities, not just at the protocol level, but also to ease physical implementation of the bus in deep-submicron technologies. LSI Logic is already implementing targeted peripherals and subsystems based on the draft AMBA 3.0 standard.”

Circuit Semantics Inc. announced that Telairity Semiconductor, Inc. has chosen Circuit Semantics' DynaCell and DynaCore as characterization solutions for its intellectual property (IP) design flow. Telairity design engineers use DynaCell to automatically characterize standard cell libraries for timing and power - the libraries are then used as building blocks for proprietary IP designs. Telairity's IP is designed to achieve specific timing goals. DynaCore is used to measure, verify and report timing for the block-level design. DynaCore uses the combination of a characterization engine and a static timing engine to provide accurate, automated timing results. Initial applications will be targeted for the communications and consumer markets.

Esterel Technologies announced 30 additional universities have joined the company's academic program since March 2002, for a total of 50 universities worldwide. Esterel's donations to these universities exceeds $37.5 million. Under the program, participating universities may license up to 20 seats of Esterel's SCADE and up to 20 seats of Esterel Studio at no charge, provided that the software is used for educational purposes only. The program enables students to learn how to design and verify embedded software and automatically verifiable RTL. New program enrollees include among others U.C. Santa Cruz, University of Minnesota, Embry Riddle Aeronautical University, Tata Institute of Fundamental Research, Université de Bretagne Occidentale, ENSTA, Ecole Centrale de Lille, University of Calgary, Linkoping University, and Ecole d'ingénieurs de Genève .

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