Scott Sandler, President and CEO at Novas Software Inc. - “The best thing I can say about 2002 is that it was better than 2001! Novas actually had a good year, but business still feels like we're driving in a blinding snowstorm - with sunglasses on - at night. We keep hoping the weather's going to clear, only to be hit with another squall. When it finally clears, the trick is going to be not going off the road because we're blinded by the sun. At Novas, we're using this crazy ride to get better at what we do - keeping our focus on our customers, our technology, and our people. Hopefully, that light in the distance is the sun breaking through!”
Altium Ltd. announced the availability of an expanded feature set for its Protel DXP board-level design system. The release of Service Pack 2 adds the full range of nVisage multi-dimensional design capture capabilities to Protel DXP and improvements to the corresponding PCB design capabilities, including interactive impedance-controlled routing and more efficient pre- and post-layout signal integrity analysis. The process of running signal integrity analysis prior to board layout has been streamlined to require only the input of the required characteristic trace impedance. The PCB editor now includes a rule type that takes the desired impedance as input and automatically calculates appropriate track widths as the designer routes. Impedance-controlled routing makes it possible for a designer to maintain optimum signal integrity conditions during board design and minimize post-layout changes.
Applied Wave Research, Inc. and WIN Semiconductors Corp. announced the availability of a process design kit (PDK) supporting WIN's pseudomorphic High Electron Mobility Transistor (pHEMT) GaAs foundry process. The PDK provides monolithic microwave integrated circuit (MMIC) engineers using AWR's Microwave Office 2002 design software, with a circuit simulation and layout environment for designing with WIN's 0.15-micron process. Applications for these designs range from broadband communication, to optical fiber communications, automobile radar, and homeland security systems.
Circuit Semantics, Inc. (CSI) announced that NurLogic Design, Inc. has adopted CSI's DynaCell product for timing and power characterization of their standard cell libraries. NurLogic's high-speed standard cell and I/O library elements provide high-performance IP to the communications and high-end computing markets.
IBM and Synopsys, Inc. announced that they are working together to produce a design reference flow for IBM's 0.13-micron process technology. The reference flow will provide foundry services customers with a path from chip design to production, using Synopsys' tools and design services and IBM's advanced manufacturing processes. IBM's relationship with Synopsys is part of an IBM strategy to make IBM's advanced chip-making technology available through high-volume chip manufacturing services. IBM and Synopsys are basing the RTL-to-GDSII reference flow on a suite of Synopsys' IC implementation and analysis tools, including Floorplan Compiler for design planning, Physical Compiler for unified synthesis and placement, and Astro for physical implementation.
The flow supports the Liberty open source format and other standard formats that allow it to be augmented with tools from other EDA vendors. The companies are validating the reference flow in silicon using a test chip that incorporates technology from several sources, including IBM, Synopsys, ARM Ltd. and Artisan Components, Inc. The reference flow is planned for availability after validation of the first test chip in the first quarter of 2003. As a result of the collaboration between the two companies, Synopsys has been awarded Advanced Business Partner status within IBM's PartnerWorld for Developers.
Additionally, IBM and Xilinx, Inc. announced a major step toward production of a 90-nanometer chip. Using IBM's copper-based 90-nanometer semiconductor manufacturing process technology, the companies have taped out a new Xilinx FPGA chip design for production in IBM's new 300-mm chip fab. The new process technology has resulted in a 50-to-80 percent FPGA chip-size reduction. IBM plans to manufacture the new product line in volume in the second half of 2003 at the company's 300-mm plant in East Fishkill, N.Y. The new facility began operation this year and will be ramping up in capacity throughout 2003. Xilinx is predicting that its investment in the new manufacturing technology will drive company pricing down to under $25 for a 1-million gate FPGA.
Infineon Technologies AG announced one year after the start of volume chip production on 300-mm wafers, the company now produces at a lower cost per chip on 300-mm wafers than on 200-mm wafers. The cost crossover was reached at the Dresden, Germany, fabrication plant. The plant will ramp to full capacity by summer 2003. Operating at full capacity, the 300-mm plant in Dresden expects 28,000 wafer starts per month. Infineon currently produces around 19,000 wafers per month in 300-mm technology in Dresden. The company has achieved a more-than-90-percent yield on the “golden wafer.” Series production of 256-megabit memory chips in the 300-mm plant in Dresden is currently based on 0.14-micron technology. The introduction of the next generation with 0.11-micron feature sizes is planned for 2003.
Magma Design Automation, Inc. said it will distribute advanced technology libraries developed by Taiwan Semiconductor Manufacturing Company (TSMC). The distribution agreement allows Magma to offer TSMC's 0.13-micron and Nexsys 90-nanometer libraries to both companies' mutual customers, integrated with Magma's design automation software. Magma and TSMC worked together to validate the libraries in Magma's design environment, from RTL to GDSII. Magma software supports TSMC's manufacturing rules for 90-nanometer technology via farm rules and metal rules for nine layers of metal routing. The integration of Magma's design flow with TSMC's libraries resulted in some optimization of the TSMC libraries.
Also from Magma - The company introduced Blast Fusion APX Advanced Physical Design System for high-performance, complex nanometer designs. The product provides a complete netlist-to-GDSII flow including placement, routing, timing and extraction, with double the capacity and a 50-percent smaller memory footprint than the previous releases. It also includes low-power design and timing analysis capabilities addressing nanometer process requirements during implementation. Version 3.1 has been successfully tested on customer designs. To enable the capacity, runtime, and memory footprint improvements, Magma implemented new algorithms and optimized the structure of the data model, while extending the timing engine to include on-chip variation (OCV) effects. OCV analysis is performed during the IC implementation flow, rather than during a post-layout timing verification phase.
Mentor Graphics Corp. announced it has signed Siemens CES Design Services as its first European FPGA Advantage Solutions Thrust (FAST) Partner. The FAST Partner Program equips FPGA service providers with Mentor's FPGA Advantage tool suite and provides assessments, training, and certifications in FPGA design methodologies from Mentor Consulting.
Also from Mentor - The company announced that Goyatek Technology Inc. has standardized on Mentor's design-for-test (DFT) tools, including MBISTArchitect (memory built-in self-test tool) and BSDArchitect (boundary scan automation tool). Goyatek is a provider of TSMC-based SoC/ASIC services and IP and is the first TSMC design services partner to support and complete both 0.18-micron and 0.25-micron designs. The MBIST Full-Speed feature accelerates traditional at-speed testing by applying a pipelining technique to simultaneously apply patterns, read them back, and compare the results. The BSDArchitect tool reduces development time by automating the implementation of boundary scan circuitry.
Numerical Technologies, Inc. announced that Samsung Electronics Co., Ltd. has signed an agreement to license Numerical's phase-shifting technology for the production of its newest advanced SRAM product. The agreement comes after a research and development engagement during which teams from both companies worked together to refine the .12-micron manufacturing process for the product. Production of the device is expected to commence in early 2003. Numerical's phase-shifting technology enables semiconductor manufacturers to fabricate subwavelength ICs using available optical lithography equipment and has been used to fabricate 90-nanometer transistors in a research environment using 248-nanometer lithography equipment.
The OpenAccess Coalition, a group of electronics companies focused on creating a standard for true interoperability among IC design tools, announced that three companies - Tektronix Inc., Celestry Design Technologies, and Mitsubishi Electric Corp. - have joined the OpenAccess Coalition. OpenAccess is an open standard API/database solution for the creation of an interoperable infrastructure for electronic design technology. Steve Schulz, President and CEO of Silicon Integration Initiative Inc. (Si2), said, “At Si2, we are extremely excited with the volume of quality companies that have joined the OpenAccess initiative this quarter. This increase in membership demonstrates the importance the industry has placed on supporting an API/database solution, which offers both interoperability and scalability.”