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Also from Atmel - The company announced an ultra-compact CMOS camera module, the Eye-On-Si for mobile phone and PDA applications. Eye-On-Si is the first product in a CMOS imaging product family that includes CIF, VGA, and megapixel sensors to be introduced throughout 2003. Eye-On-Si is a complete digital camera in less than 1/2 cubic cm and includes a single chip (sensor and image processor), a lens, a flexible cable, and all necessary peripheral components. The product is built on an Atmel package measuring 9.5x9.5x4.95mm. It is a 1/7-inch optical form on CMOS camera chip with 352x288 pixels. The module operates with a single 2.5V power supply within a frequency range from 3MHz to 80MHz. The on-chip image processing is based on Atmel's AVR technology. Most of the on-chip functions such as auto white balance, auto exposure control, color correction, flicker detection, and correction are programmable through a 2-wire serial interface. Atmel will also introduce in 2Q 2003 a camera module in VGA format that will have the same image quality, low size, image processing flexibility, and low power consumption as the Eye-On-Si product.

Cadence Design Systems, Inc. and Xilinx, Inc. announced the adoption of the Xilinx RocketIO Design Kit for SPECTRAQuest by 500+ designers and engineers. The kit is an electronic blueprint for simulating and implementing Virtex-II Pro Rocket IO transceivers in a system. The Xilinx RocketIO Design Kit is for the design, implementation, and verifications of GHz-speed serial links using multi-gigabit I/O technology, and for developing optimal constraints for PCB systems to drive PCB floorplanning, routing, and verification process. The design kit includes the following: system-level topologies for use of the device on the board/system; verified I/O buffer models; a large package model; testbench data, correlation data; connector models for backplane applications; and device specific scripts/tools to evaluate simulation results.

Also from Cadence - The company announced that Texas Instruments (TI) has selected Cadence First Encounter physical prototype and placement system for use worldwide by its ASIC team. TI will integrate First Encounter into its flow for ASIC designs for the partitioning and time budgeting of high-performance ICs. TI also has integrated Cadence CeltIC into its ASIC design flow for sign-off crosstalk glitch analysis, and completed qualification work of Cadence's 64-bit 4.0 NC-SIM for chip simulation.

Concept Engineering announced the release of SpiceVision PRO, a turbo version of SpiceVision, an interactive visualization tool to debug and analyze SPICE circuits and models. Unlike SpiceVision, SpiceVision PRO is not limited to a certain number of components. SpiceVision PRO includes 64-bit support, a high-speed database for larger designs, and a tcl-based UserWare API. SpiceVision PRO fits into any EDA environment where SPICE design files are used to verify circuit behavior. It produces transistor-level schematics from complex SPICE descriptions to help visualize parasitic effects. SpiceVision PRO generates schematics from pure SPICE connectivity information using Concept's transistor-level schematic engine.

Cypress Semiconductor Corp. announced that it is sampling the POSIC2G framer (CY7C9537), a 2.5 Gbps channelized SONET/SDH framer with Generic Framing Procedure (GFP). POSIC2G provides support for both resilient packet ring (RPR) protocol operation at OC-48/STM-16 (2.5 Gbps) rates and solutions for existing data transport infrastructure, as well as efficient RPR mapping with GFP. RPR technology is designed for efficient transport of packet data over a ring topology. This technology simultaneously supports traditional carrier-class features such as performance monitoring, resiliency, and data restoration, as well as newer services for packet data and latency sensitive traffic.

HP introduced two new servers, the HP ProLiant DL740 and the second-generation HP ProLiant DL760. The servers include the HP F8 chipset, hot-plug RAID memory, and HP ProLiant Essentials management software. The company says the servers are appropriate platforms for high-performance, database, and business applications. The HP F8 chipset is based on a symmetric multiprocessing architecture and combines PCI-X I/O technology, Gigabit Ethernet, Ultra3 SCSI, and the Intel Xeon processor MP. The company also says the ProLiant servers offer fault tolerance and availability, which are important, as Microsoft Windows Server 2003 and Linux increase addressable memory.

Also from HP - The company has added two PCs to the HP Pavilion desktop line - the HP Pavilion 754n and 764n, which includes a DVD+R/+RW and a six-in-one media card reader, for under $1000. The six-in-one media card reader, positioned on the front of the PC, allows users to transfer data from all common flash media formats. Additionally, the 764n includes a NVIDIA GeForce MX 440 graphics card and 128 MB DDR graphics memory.

Again from HP - The company announced the HP super-scalable processor chipset sx1000 and the HP mx2 dual processor module using Intel Itanium 2 processors. The company says the products enable enterprise customers to keep IT costs down by scaling performance in existing servers - the chipset and module scale the size of HP servers using Itanium 2 processors and double the number of future Itanium 2 processors that can be used in an HP server.

Infineon Technologies AG announced the availability of a family of unbuffered DIMMs (dual-in-line memory modules) in 128MB, 256MB and 512MB densities. Based on 256Mb (megabit) Double-Data-Rate 400 Mbps (DDR400) memory, the modules are compliant with Intel specifications and designed to meet the requirements of the proposed JEDEC PC3200 3.2 GBps (gigabyte-per-second) bandwidth specification for use in the main memory of high-performance desktop PCs and workstations. The PC3200 DIMMs and memory chips are immediately available, and are produced in 0.14-micron process technologies and in production volume at Infineon's 300mm and 200mm DRAM fab cluster.

InnoLogic Systems, Inc. announced that STMicroelectronics is using InnoLogic's ESP-CV to eliminate functional bugs in its embedded memories that are included in product lines in telecom and data communications, consumer and automotive electronics. ESP-CV verifies the functional equivalency of full custom designs across various levels of abstraction. STMicroelectronics reports its designers were able to find and fix functional bugs and streamline the verification of compiler generated embedded SRAM's, ROM's and DRAM's using the tool.

Intel Corp. announced plans to convert Fab 12, a 200mm wafer fab in Chandler, AZ, to a 300mm wafer fab. The conversion project, estimated to cost $2 billion, will begin in the first half of 2004 with production scheduled to begin in late 2005. The converted fab will start up production on 65-nanometer wafers. When completed, the converted Fab 12 will become Intel's fifth 300mm facility. The company currently has two 300mm fabs in operation - one in Hillsboro, OR, and one in Rio Rancho, NM. Two other 300mm facilities are under construction. One in Oregon will begin operations later this year, and a facility currently under construction in Ireland is scheduled to begin operations in the first half of 2004. Additionally, the company announced plans to sell 524 acres of land in Forth Worth, TX. The land was purchased in 1997 as part of a planned manufacturing facility. However, changes in manufacturing technology and current construction projects at existing Intel sites mean the property is no longer part of the company's future plans.

Mentor Graphics Corp. announced a PCI Express configurable controller core for development of subsystems supporting the PCI Express serial interconnect technology. To help validate functional compliance, Mentor is also providing an in-circuit emulation PCI Express verification tool, based on the VStation and Celaro emulation systems. The company says the PCI Express roadmap includes full support for the specification including endpoint, legacy endpoint, bridges, switch, advanced switches, and root complex configurations. Configurable options include the number of virtual channels, the number of lanes (up to 32) and links per port (up to 32) and the maximum payload size. Flow control is provided for different types of traffic. The first IP (intellectual property) release will be capable of supporting PCI Express Endpoints and bridges from one to four lanes in width.

In related news -- Mentor Graphics and Altera Corp. announced a reference design for the development of applications based on PCI Express serial interconnect technology. The design includes a configurable PCI Express IP core and in-circuit emulation verification from Mentor Graphics and a Stratix-based PCI card from Altera. The Mentor Graphics board illustrates a PCI-to-PCI Express Bridge application running at full speed in an Altera Stratix PLD-based PCI card. The system is designed to connect to Mentor Graphics' VStation hardware emulation platform via a parallel interface, and implements a back-to-back bridge that converts PCI through to PCI Express Protocol and back to PCI.

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