Volunteers at Our Beck & Call


Also from Mentor Graphics - The company announced enhancements to the Calibre suite of resolution enhancement technology (RET) tools the company says will ensure Calibre's RET modeling accuracy for the next three technology nodes. RET modeling accuracy becomes increasingly important in the sub-100-nanomemter nodes where the process window shrinks (parameters at which the process delivers yielding silicon). Accurate RET modeling of the complex lithographic system can help ensure pattern fidelity despite distortions that occur when IC features are one-third the wavelength of the exposure equipment.

Before full-chip RET operations, there are a number of key model calibration and creation steps. During model setup, the user inputs key parameters such as test pattern silicon measurements, exposure wavelength, numerical aperture, sigma and the illumination pattern. The enhancements to Calibre VT5 (Variable Threshold Version 5) and TCCcalc (vector, thin-film optical calculations) are extensions to the Calibre RET silicon modeling and OPC technology base. The resulting new TCCcalc optical model is fitted to the data, with resist and etch effects handled by the new VT5 model. The model's predictive ability is verified versus silicon, then used by VT5 in conjunction with batch, full-chip RET software for production.

From Mentor Graphics, as well - The company announced that the Wire Harness Technology (WHT) division of Vansco has adopted the Mentor Graphics Capital Harness Systems (CHS) family of products for the design, engineering and manufacturing of electrical wire harnesses. Vansco supplies wire harnesses to manufacturers of large transportation and heavy construction equipment. Designs for its transportation customers include buses with more than 100 harnesses per vehicle and as many as 400 circuits per harness. CHS is an end-to-end tool set for creating complex wire harnesses and includes tools to automate the design, analysis and manufacture.

Nassda Corp. announced that it has moved to new worldwide headquarters in Santa Clara, CA. The company was previously located elsewhere in Santa Clara.

Novas Software, Inc. announced it has become a corporate member of Accellera. The company says that as a member company of Accellera, Novas will promote and drive adoption of standard design representation formats.

Sandwork Design, Inc. announced enhancements to SPICE Explorer with Release 2003.1, including 64-bit capabilities, a second-generation waveform data format (WDF-II) to address file size in both large analog and digital circuit simulations, application programming extensions (APX) which include a Tcl/Perl driven scripting language for user-defined measurements or batch-mode waveform file regressions, dynamic meter enhancements to automatically measure duty cycles, eye-diagram measurements, multiple-bits AD and DA conversions, and FFT windowing functions to provide post-simulation FFT analysis.

Sequence Design has signed a sales management agreement for Aquarius Technologies to represent the company in Europe, supplementing the company's European network of FAEs, R&D and technical marketing staff. The effort will be headed by John Siemens.

Synopsys, Inc. announced additions to its verification platform including an advanced constraints solver engine for creating efficient stimulus, a coverage engine to measure the quality of the verification environment, and support for OpenVera Assertions (OVA) to provide a unified platform for assertion-based verification methodology. The technologies have been added to the latest release of the Vera testbench automation tool and are compatible with the VCS 7.0 HDL simulator. The new constraints solver in Vera permits users to implement a constraints-driven random verification methodology, and analyze solutions for hundreds of simultaneous constraints, each with hundreds of random variables. The engine is architected for compatibility with the constraints language that is being defined for Accellera's emerging SystemVerilog standard.

Also from Synopsys - The company announced that Motorola's Semiconductor Products Sector (SPS) has selected Synopsys' verification platform, including the VCS Verilog simulator and the Vera testbench automation tool, to provide verification techniques such as constraint-driven random stimulus generation, assertion-based verification, and formal analysis. Under the terms of the multi-year contract, Synopsys' Smart Verification technology and verification consultants will work with SPS. All of Motorola's semiconductor business groups plan to adopt the technology.

From Synopsys, as well - The company announced that Texas Instruments ASIC Division has completed two multi-million gate designs using Synopsys' Physical Compiler (PC) and has integrated PC into its standard Pyramid ASIC design flow. PC is a component of Synopsys' Galaxy Design Platform and unifies synthesis and placement.

And finally - Synopsys announced that Philips has signed a multi-year volume purchase agreement with Synopsys for its front-end design platform. Synopsys' platform will become a design standard at Philips' Semiconductor Division for developing complex digital ICs. Philips will use the technology for designs targeting its CMOS 12 (130 nanometer), CMOS 090 (90 nanometer) processes, and beyond (see “Philps touts Circles of Connectivity”).

Verisity Ltd. announced that Mentor Graphics Corp. is the 100th member of Verisity's Verification Alliance program. The program links Verisity with industry consultants and consulting firms to provide customers with assistance in verification of complex IC, SoC, and system designs; along with engineering resources. Mentor Consulting, the professional services division of Mentor Graphics, will provide engineers with verification methodology training and consulting services based on Verisity's solutions.

By joining the Verification Alliance program, Mentor Consulting says it is addressing increasing customer demand for training and consulting services in the verification field.

WaferYield Inc. announced that AMI Semiconductor (AMIS) has completed an initial evaluation of WaferYield's WAMA (Wafer Mapping) software and reports “encouraging” yield improvement on leading edge processes. WaferYield's Integrated Global Optimization (iGO) tools assist in Design-for-Manufacturing through optimization of wafer mapping optimization. The WAMA product family is a field/die placement tool for performing multi-dimensional analysis.



Industry News - Devices

Altera Corp. and Arrow Electronics, Inc. announced availability of the MAX 7000 Quick Start development kit for MAX 7000 complex PLDs for university students, digital designers implementing general-purpose programmable logic designs, and customers new to Altera's MAX 7000 device family. The development kit includes a development board with a MAX EPM7128AE device, the Quartus II Web Edition design software, a programming cable, an example design, power supply, and documentation.

Also from Altera - The company and Gidel announced availability of a rapid prototyping board for customers designing system-level applications with Stratix FPGAs. Gidel's PROC1S Stratix 80 board includes a Stratix EP1S80 device and is intended for prototyping and real-time emulation of high-bandwidth, high-density applications including DSPs, imaging, machine vision, video processing, aerospace, and military systems. Gidel is an Altera Consultants Alliance Program member company.

Amphion announced that Dialog Semiconductor Plc has licensed a system-level core from Amphion for use in a high-volume standard product ASIC design. Dialog develops and supplies mixed-signal technology for imaging, audio and power management. Amphion sells a range of cores for video, image, and audio signal processing in targeted-netlist formats for SoC/ASIC technologies and FPGAs. The standard set of core deliverables for an ASIC usually includes a bit-accurate C model, pre-compiled HDL simulation models, Verilog and VHDL testbenches, a gate-level netlist, and user documentation.

Atmel Corp. announced a new intelligent stepper motor driver IC, the ATA6830, manufactured using Atmel's 0.8-micron BCDMOS process technology. The new driver supports operation of up to 45 Volts and is optimized for applications in harsh environments including automotive systems, particularly cars with Xenon lights, where automatic headlamp adaptation is mandatory to avoid dazzling on-coming vehicle drivers. The company says that, in contrast to conventional stepper motor driver ICs that need a separate microcontroller for the cruise control function, the ATA6830 is a complete one-chip solution as it includes an intelligent travel operation control block to control the function.

Also from Atmel - The company announced the availability of a new standard RF product, the Intermediate Frequency (IF) demodulator ATR0797, designed for a range of communication infrastructure systems such as fixed wireless or broadband wireless access applications. The ATR0797 is for use in the receive path of a wireless system where it converts IF bandpass signals to complex bandpass signals with a minimum of signal distortion. It is manufactured using Atmel's SiGe technology, and has two buffers integrated at the IF input for three switchable gain steps.

Again from Atmel - The company announced the Access Point/router (AT76C511) as an addition to its VNET2 family of wireless LAN products. The AT76C511 is a single-chip with two ARM7TDMI processors, two 10/100 Ethernet MACs, a high-speed USART, and a 802.11b MAC for connection between a wireless LAN and a WAN. The device is a based-bridge controller and supports access point (AP), bridges, wireless routers, and ADSL to WLAN. In AP mode, the internetworking ARM manages the Ethernet based data that is destined outside the WLAN using IP over Ethernet. In Bridge mode, the internetworking ARM implements protocols for bridging AP's to AP's. In a wireless router mode, the second Ethernet MAC can be connected to a 4-port or 8-port Ethernet switch. Additionally, the second Ethernet MAC can also be connected to an ADSL chipset. The company says that to address “today's security concerns,” the AT76C511 integrates a dedicated hardware block to implement Wired Encryption Privacy (WEP) enciphering/deciphering of wireless data for both 64- and 128-bit keys.

« Previous Page 1 | 2 | 3 | 4 | 5  Next Page »



Review Article Be the first to review this article
CST: Webinar October 19, 2017

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
FPGA Engineer for Teradyne Inc at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Upcoming Events
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise