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ARM is also partnering with Cadence Design Systems, Inc. through a new five-year agreement "targeting design-chain optimization for their mutual customers." ARM is providing access to their IP to facilitate design and verification using Cadence tools on ARM core-based SoCs. Customers will be able to incorporate different ARM cores into Cadence's Incisive verification platform. The two companies say they are currently working on design chain interoperability via standardized models and validation suites for ARM's AMBA bus using the SystemC modeling language. Cadence is a member of ATAP (ARM Technology Access Program).
Meanwhile, from Cadence - the company announced enhancements to its CeltIC 4.1 signal integrity product, part of the Encounter IC design platform. The company says the enhanced software is faster than previous versions, and includes overshoot-undershoot glitch analysis for sub-130-nanometer technologies and a timing engine for timing window convergence. CeltIC 4.1 can also generate compatible timing windows for delay analysis with third-party tools.
Additionally, Cadence announced it has joined the FlexRay Consortium as a tool development member. The FlexRay Consortium is an organization formed in September 2000 to drive the adoption of an open standard for high-speed bus systems for distributed control applications in automobiles, such as x-by-wire.
CAST, Inc. announced two new IP cores implementing networking and bus standards, including the 1-Gigabit Ethernet media access controller (MAC-1G), and the USB version 2.0 function controller (CUSB2). The company says the new cores intend to provide a "cost-effective" method for designers to incorporate high-speed Ethernet or USB features into designs. The cores are designed for reuse, are delivered with verification tools and documentation, and are available in source form for ASIC synthesis or as netlists optimized for various programmable devices. The CUSB2 and MAC-1G will ship in April 2003 and May 2003 respectively.
ChipVision Design Systems, AG, announced a new version of ORINOCO, a design tool for optimizing chip-power consumption at the specification level. The company says the tools reduces power and decreases design time compared with RTL methods by working at the architectural level early on in the design process. In addition to existing design entry levels (using C/C++), ORINOCO will now support SystemC as well, via a SystemC user interface. A beta version of the new SystemC front-end was shown at DATE 2003 in Munich last week.
CoCreate Software, Inc. announced that Leviton Manufacturing Co. will deploy the company's OneSpace Collaboration to all of its U.S. and overseas manufacturing facilities. Leviton says it expects to reduce costs and streamline development by extending its current use of CoCreate technology to development and design staff throughout the company.
CoWare announced new versions of the LISATek EDGE processor designer, RIM software designer, and HUB system integrator tools, which include support optimized for integration with the CoWare N2C design environment. The new release also includes Memory Explorer, which lets system designers explore, analyze, and change the configuration of caches, buses, and memories during complied simulation runs. The compiled ISS model, "based on patent-pending Just-in-Time Cache Compiled Simulation technology," allows for the optimization of the memory subsystem. The company says the technology supports self-modifying code typical of an RTOS. The LISATek Macro Assembler was also announced and provides features, which the company says are similar to a high-level programming language, including complex macros that can be called like processor instructions. CoWare recently acquired LISATek, Inc.
E*ECAD, Inc. announced that it has signed a distribution agreement with Solution-Soft Systems, Inc., whereby Solution-Soft will sell its GDSII compressor, gdzip, through E*ECAD's on-line sales channel using time-based licensing. Solution-Soft's gdzip compresses GDSII files to reduce transfer time by creating block-by-block checksums during compression to verify that the decompressed file is identical to the original.
HARDI Electronics AB announced version 2.1 of the HARDI ASIC Prototyping System (HAPS), for real-time speed and debugging. The new release allows for up to 8 million ASIC gates running at 200+ MHz on a single board. To accommodate larger designs, customers can also stack several boards. The HAPS ASIC prototyping platform includes FPGAs for implementing ASIC logic, connectors for adding IP-blocks, clock nets for high-speed, configurable connectivity for partitioning, and I/O connections. It is designed to support any ASIC, without modifications.
Novas Software, Inc. has extended its Verdi Behavior-Based Debug System to support "emerging assertion-based verification methods." The company says the new release integrates assertion languages and the results of assertion-based verification tools for the debug and analysis of complex ICs and SoC designs. Verdi enhancements are based on compiler and database extensions to Novas' Design Knowledge Architecture, and provide interoperability with third-party assertion-based verification tools.
Mentor Graphics Corp. announced a collaboration with Xilinx, Inc. and Thales Communications to develop a new FPGA verification flow to meet Thales' product development requirements. Xilinx will extend its existing EDA Partner Alliance agreement with Mentor Graphics, to include the FormalPro equivalence checking technology, ModelSim HDL simulation, and Precision Synthesis. The collaboration is intended to provide an integrated FPGA methodology to aid Thales in the development of next-generation military and aviation electronics.
Open Core Protocol International Partnership (OCP-IP), an industry association working on standards for IP core interfaces, announced the availability of the OCP Specification 2.0 release candidate. The specification includes a model for write transfers for precise end-to-end-responses, an enhanced burst model for both burst length and packet-style transfers, and support for user-defined in-band command data and response extensions which can be used to support features such as parity and Error Correcting Codes (ECC). The specification also makes provisions for "lite-weight" OCP interfaces with read-only/write-only/FIFO-style IP cores, as well as support for "lazy memory" synchronization.
Sequence Design announced CoolTime technology as the basis for an instantaneous voltage-drop analysis tool that will be added to the company's electrical-integrity analysis tools for SoC design. The company says CoolTime analyzes power, voltage drop, timing, and signal integrity concurrently by examining the dynamic effects resulting from power-grid capacitance, package inductance, and on-chip decoupling capacitors. In instantaneous mode, the tool runs at 2 million gates per hour. In static mode, it run at 25+ million gates per hour. The technology will be available commercially in Q2 2003.
Synopsys, Inc. and Applied Dynamics International (ADI) announced a real-time physical simulation environment for automotive design, which links Synopsys' Saber simulator with ADI's SIMsystem HiL equipment, for real-time verification of automotive system designs. The two companies say that, traditionally, automotive designers have had to build hardware prototypes for all of the mechanical, hydraulic, and electrical components used in a car's subsystems, and then combine these prototypes to simulate and verify the functionality of the entire car. Linking Synopsys' Saber simulation environment with ADI's SIMSystem HiL equipment is intended to replace the need for hardware prototypes and, therefore, reduce the time required to simulate car subsystems, including the power train, the anti-lock braking systems, and the brake-by-wire, steer-by-wire, and throttle-by-wire systems.
Synplicity Inc. announced it has signed a joint development agreement with NEC Electronics Corp. to provide support for NEC's Instant Silicon Solution Platform (ISSP) ASIC devices. Under terms of the agreement, Synplicity will develop custom synthesis mapping technology for its Synplify ASIC software optimized for the ISSP devices. NEC Electronics has provided Synplicity with detailed information about its ISSP architecture, validated the Synplify software's performance, and will integrate the software into its overall OpenCAD design flow. NEC Electronics and its subsidiaries in North America and Europe will offer library support for the custom Synplify software to its ISSP customers worldwide. As part of this joint agreement, Synplicity will train and work with NEC's field design centers to provide support. Additionally, Synplicity intends to develop future releases of the Synplify ASIC software in conjunction with NEC Electronics.
Telairity Semiconductor and Icinergy Software announced that Icinergy's SOCarchitect technology will be packaged with Telairity's high-performance ASIC design kit as the virtual prototyping environment for Telairity customers to perform physical design planning and timing estimation. The two companies collaborated to create a customized design solution that fits the specific needs of Telairity's ASIC design flow. Telairity is a fabless ASIC company providing tools, methodology, hard IP and services. Icinergy Software provides tools for complex IC and SoC design.
TransEDA PLC. announced a new release of VN-Property Checker and Analyzer, which now supports the Accellera Property Specification Language (PSL), formerly known as IBM Sugar. Udo Muerle, CEO at TransEDA said, "TransEDA is an active member of the Accellera committee and recognizes the tremendous value that this powerful and user-friendly industry standard language brings to our customers and the industry at large. We have quickly adopted the new language into our R&D, and are proud to be the first EDA vendor to launch a property checking solution based on Accellera PSL." VN-Property is part of TransEDA's Verification Navigator integrated design verification environment, and combines formal verification and simulation.
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