Show me the money

Meanwhile, Mueller explained how design strategies have evolved in dealing with power: “For many years, there have been tools available to get power estimations up-front without physical knowledge of the circuit through RTL power analysis and prediction. Then there were early vector-based dynamic solutions that were only usable on small blocks of the design. Following on that, tools for cell-based static power analysis were developed, which allowed you to consider the full-chip physical layout, but only as a resistive network using average currents based upon the estimated toggle rates of various blocks. This technology has been part of the standard sign-off flow for designs for many years. But now speeds are much higher, voltage supplies are much lower, and capacitance and inductance are much more important in determining yields and power grid integrity. [However], static tools can't look at the impact of decoupling capacitance, on-chip inductance, or package inductance.”

“The other main issue with the current design flow is that this power analysis is typically done in the verification stage of the design. If you find anything wrong at this stage, it is extremely painful to fix. The result is that designers must over-design the power grid just to avoid any potential surprises during verification. But when you over-design, there is a die size and routing resource penalty for the power grid. It's an extremely complex problem to accurately analyze the full chip to determine the transient dynamic effects of simultaneous switching of outputs, and the impact of both intrinsic and intentional on-chip decoupling capacitance. Even at 0.18 micron, customers have come to us with simultaneous-switching design failures. Low-power designs require particularly thorough analysis, with large blocks switching on and off. Most people use some form of ad hoc on-chip solution such as the use of filler cells or blank space for decoupling.”

“We attack this problem by taking as much of the physical design information into [Apache] RedHawk, as is available to the designers at that particular point in the process. If there's only initial first-pass placement without routing, we can provide early feedback to the design team about power grid requirements and potential static and dynamic hot spots. As you refine the data throughout the design flow, the tool provides increasingly accurate results all the way through to final verification sign-off.”

(Editor's Note: Apache Design will be presenting a hands-on tutorial at DAC 2003, as will Sequence Design, Cadence Design Systems, IOTA Technology, Synplicity, Sigrity, Magma Design Automation, Mentor Graphics, Xilinx, and NPTest. The majority of those tutorials will be addressing issues related to power and signal integrity. Meanwhile, you might also want to attend the day-long tutorial on Monday at DAC 2003 entitled, “Design Techniques for Power Reduction” organized by Borivoje Nikolic from the University of California.)

Three rumors and a factoid

(Editor's note: The three rumors below hail from various anonymous sources. The factoid, however, hails from Dave Evans at Forte Design.)

Rumor No. 1 - “EDA people don't party as much as they used to at DAC because we're an aging population.”

Rumor No. 2 - “I hear they're floating the idea of restarting ISD Magazine.”

Rumor No. 3 - “There's 75 million square feet of vacant office space right now in Silicon Valley.”

Factoid - “No matter how much randomness critics may sense in the EDA process - different point tools, companies, etc. - the results we've achieved over time have been simply staggering.”

« Previous Page 1 | 2 | 3 | 4 | 5 | 6             

Review Article Be the first to review this article

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy