Show me the money

Meanwhile, Mueller explained how design strategies have evolved in dealing with power: “For many years, there have been tools available to get power estimations up-front without physical knowledge of the circuit through RTL power analysis and prediction. Then there were early vector-based dynamic solutions that were only usable on small blocks of the design. Following on that, tools for cell-based static power analysis were developed, which allowed you to consider the full-chip physical layout, but only as a resistive network using average currents based upon the estimated toggle rates of various blocks. This technology has been part of the standard sign-off flow for designs for many years. But now speeds are much higher, voltage supplies are much lower, and capacitance and inductance are much more important in determining yields and power grid integrity. [However], static tools can't look at the impact of decoupling capacitance, on-chip inductance, or package inductance.”

“The other main issue with the current design flow is that this power analysis is typically done in the verification stage of the design. If you find anything wrong at this stage, it is extremely painful to fix. The result is that designers must over-design the power grid just to avoid any potential surprises during verification. But when you over-design, there is a die size and routing resource penalty for the power grid. It's an extremely complex problem to accurately analyze the full chip to determine the transient dynamic effects of simultaneous switching of outputs, and the impact of both intrinsic and intentional on-chip decoupling capacitance. Even at 0.18 micron, customers have come to us with simultaneous-switching design failures. Low-power designs require particularly thorough analysis, with large blocks switching on and off. Most people use some form of ad hoc on-chip solution such as the use of filler cells or blank space for decoupling.”

“We attack this problem by taking as much of the physical design information into [Apache] RedHawk, as is available to the designers at that particular point in the process. If there's only initial first-pass placement without routing, we can provide early feedback to the design team about power grid requirements and potential static and dynamic hot spots. As you refine the data throughout the design flow, the tool provides increasingly accurate results all the way through to final verification sign-off.”

(Editor's Note: Apache Design will be presenting a hands-on tutorial at DAC 2003, as will Sequence Design, Cadence Design Systems, IOTA Technology, Synplicity, Sigrity, Magma Design Automation, Mentor Graphics, Xilinx, and NPTest. The majority of those tutorials will be addressing issues related to power and signal integrity. Meanwhile, you might also want to attend the day-long tutorial on Monday at DAC 2003 entitled, “Design Techniques for Power Reduction” organized by Borivoje Nikolic from the University of California.)

Three rumors and a factoid

(Editor's note: The three rumors below hail from various anonymous sources. The factoid, however, hails from Dave Evans at Forte Design.)

Rumor No. 1 - “EDA people don't party as much as they used to at DAC because we're an aging population.”

Rumor No. 2 - “I hear they're floating the idea of restarting ISD Magazine.”

Rumor No. 3 - “There's 75 million square feet of vacant office space right now in Silicon Valley.”

Factoid - “No matter how much randomness critics may sense in the EDA process - different point tools, companies, etc. - the results we've achieved over time have been simply staggering.”

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