Down but not out in Silicon Valley

“Socware Design Cluster, which is headed and promoted by ISA, was established in 2000 as a consortium between the three main universities in Sweden (Linköping University, Lund University and Royal Institute of Technology) and the Acreo Research Institute for Microelectronics. These four entities decided to team up with ISA and invest in a public infrastructure for research into SoC design, which they appropriately saw as a crucial core technology for the wireless industry - which is, in turn, an industry that has been pivotal for the economic health of Sweden. Just look at Nokia and Ericsson, if you doubt that.”

“The Socware Design Cluster then successfully arranged for government sponsorship as well - along with funding from other authorities and foundations interested in the technology. The program was structured to fund a new Masters program and new Ph.D. research projects. In addition, funds where made available for industry partners to join or initiate special research projects. Industry partner investments are rewarded with access to any IP that might emerge from the project. Such IP can be used in any products the company chooses to use it in, but can not be resold as a stand-alone product.”

“Our initial emphasis was on education. We started in 2000 with 50 students in our Masters program, but this year expect up to 200 students - all working toward an advanced degree in engineering with an emphasis on system-on-chip design. Besides this, we have 70 Ph.D. students. Approximately 50% of our students are from other countries, in particular India and China. However, all of our students come out of the program well prepared to address the technical challenges associated with system design, in particular the RF and embedded software issues that are pivotal to wireless chip sets.”

“We are not concerned about expending energy educating foreign students. When the economy is strong, the students often settle here in Sweden and add to our technical brain trust. We also receive great benefit from our talented Ph.D. students. However, even if the students return to their home countries, we consider our efforts to be worthwhile as we believe these graduates become permanent good will ambassadors for Sweden.”

“Meanwhile, we know there are lots of companies who want to be part of our 'Wireless Valley' in Kista - where there are 25.000 people focusing on wireless system design - but some companies may not be ready yet to invest in the Socware Design Cluster. So we are able to offer them a position in various Research Demonstrators hosted by the Institute, and created from various Ph.D. research projects - projects such as software-defined radios, for instance, designed to integrate a transceiver front end for multi-mode and multi-standard applications.”

“For such companies, the Institute may recruit and incubate a professional team for a certain period until the team knows 'how to fly' - and then the company takes over. The Institute, therefore, acts as a gateway, which offers support to international companies wanting to invest in our emerging Socware Design Cluster.”

Issues at DAC - Design for Yield

ChipMD has just opened its doors, and the staff is understandably riding high on the adrenaline associated with a new start-up. Dale Pollek is CEO of the new company and says that the focus of the soon-to-be-released tools will be one of the crucial problems in analog and mixed-signal design - Design for Yield (DFY). Ravi Ravikumar is Vice President of Business Development for the company. I spoke with both of them last week as they helped to distinguished between DFY and DFM (Design for Manufacturing).

Pollek said, “Current solutions in DFM are focused very late in the design flow; starting from post layout and extending into the manufacturing steps. Yield is usually only considered after the first silicon is manufactured. DFY is distinguished from DFM by the fact that it forces designers to think about yield issues in their products at the very start of the IC design process. Yield is an IC-sensitive issue for all designs, whether pure digital, memory, mixed-signal, or pure analog/RF. At 130 nanometers and below, for instance, you might have 20 different possible types or layouts of transistors, each reacting differently to operating conditions and process parameters, such as temperature, voltage, oxide thickness, etc. You need to know in advance how these different design choices would function in real-world operating conditions in order to adjust your design parameters and maximize yield, before you cut your first masks.”

“How do you do that? You examine the process data that's readily available from your fab process people for your particular process technology, which gives you a fixed operating window for the device under development. Then, in order to make sure your device will deliver to specifications across all the combinations of these parameters and conditions, you need to reduce the impact of it all on yield. With the number of parameters involved, the traditional 'four corner' worst-case analysis will not provide you all of the key worst-case conditions. So, you must think out of the box.”

“Typically, designers are forced by time to market pressures to complete a design quickly - and design for yield is seldom a consideration until after first silicon. Then the design is rushed into manufacturing without fully considering the impact of the process. Some call this 'throwing the design over the wall' into manufacturing. Today's reality is such that time to market pressures require this strategy. Meanwhile, the complexities of understanding manufacturing issues have simply been too difficult to provide to design in a feasible method.”

Ravikumar said, “So we want to promote DFY by remembering that each circuit is required to operate within a specified operating region, which is in turn governed by pre-defined parameters such as voltage, temperature, etc. The circuit is then designed under the default or nominal process, voltage and temperature conditions - also known as the nominal operating point. Designers then do the traditional 'four corner' worst-case analysis to increase their confidence that the device will operate in the entire feasibility region. Implied in this is the fact that the operating region of the design and the feasibility region of the process technology used will match, to create a functional design across the entire range of parameters. Designers don't usually think about the process technology used - or yield - until after first silicon. Hence you see the problems with parametric yield.”

“DFY has almost always been an afterthought in design flows. This won't work anymore, now that masks are so expensive and development costs so high. Lost revenue and market share due to yield is at least an order of magnitude higher than these development costs. Lost yield is lost money. The typical design is set for the nominal process parameters that represent the ideal or golden processing conditions - but ideal conditions just don't exist in the real world.”

“Meanwhile, as process technologies emerge at 130 nanometers and below, you've got increasing process variations from die to die, lot to lot, and even high variances within the die itself, as you manufacture products. This means 'like parts' of the design may not actually perform 'close enough' to each other - a critical problem for dealing with timing, but even more critical in the RF/AMS world where you must have as close to matching results as possible. For digital designs, you might find you can just add larger guardbands and get to a working device. However, for AMS designs, you will need to keep within 3 sigma of the ideal conditions, to keep your yield adequate. In fact, some designs, such as large memories, will require you 'design in' up to six-sigma quality or beyond, as you can't afford one transistor to function differently when you have Giga-sized memories. Therefore, RF, analog and mixed signal design is most sensitive to all the DFY considerations.”

Issues at DAC - FPGA EDA

Simon Bloch, formerly of Aristo Technologies, is now general manager of the FPGA Design Solutions division at Mentor Graphics Corp. in San Jose. He was willing to speak by phone for a few minutes last week and describe (with palpable enthusiasm) the future of the FPGA market and those vendors who are able to support it going forward.

“After the merger, I continued to follow the FPGA market with great interest. I decided to join Mentor to focus on FPGA design because I saw the trend of designers choosing FPGAs in favor of ASICs and I felt that Mentor had the right pieces to appropriately service and grow the tool market.”

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