Down but not out in Silicon Valley
- Effective work in progress design management software
- Timely collaboration between sourcing and manufacturing
- Library and data management
- Collaboration around Bill of Materials
- Integration into a company's enterprise management tools
- Configured to be added to company's infrastructure
- Ease complexity of collaboration across various corporate firewalls and companies with divergent core competencies.
- Secure high-volume data exchange
- Efficient change management across the design chain
No doubt, the joint announcement and the strategic thinking behind it, does knit together a variety of concepts and technologies to create a rational fabric for design, collaboration, and increased product development and manufacturing efficiency. Don't think for a minute, however, that they're not going to have a lot of competition in this arena. There are similar offerings addressing all the various parts of this equation in existence today emanating from a plethora of companies. It will only be a matter of time before some subset of those diverse offerings are similarly knit together via corporate joint ventures to take on the triumvirate announced on the 21st.
Celoxica Ltd. announced support for the 90-nanometer Spartan-3 FPGAs from Xilinx, Inc. The companies said that by combining the Celoxica DK Design Suite with platform FPGAs such as Spartan-3, designers can efficiently implement high-density, low-cost programmable systems that include millions of gates and soft processor cores, including Xilinx's MicroBlaze. Additionally, Celoxica announced that Chunghwa Telecom Co., Ltd. has adopted Celoxica's DK Design Suite and RC2000 development boards.
Chartered Semiconductor Manufacturing and Mentor Graphics Corp. announced a collaboration to deliver IC analog/mixed-signal (AMS) design kits validated for various Chartered manufacturing processes, starting with 0.18 micron and then extending from 0.13 micron to 90 nanometer. The Mentor AMS design kits are available at no charge and allow the IC design workflow to be tailored for the Chartered RF CMOS process. The kits provide all foundry data files and models for use with front and back-end IC design tools from Mentor Graphics. Designers can work within Mentor's AMS tool flow, or move between Mentor's Calibre design platform and front-end design products from other EDA providers.
CPU Technology, Inc. and Magma Design Automation announced they have signed a long-term licensing agreement for Magma's physical design tools. The companies say the licensing agreement will allow CPU Tech to adopt a COT model for its deep-submicron SoC designs. CPU Tech will interface its front-end, system-level modeling and design tools to Magma's back-end placement and routing tools.
Emulation and Verification Engineering (EVE) announced that Canon Information System Research of Australia (CISRA) has chosen ZeBu, EVE's verification platform, to verify and debug a new line of ASICs. CISRA says it evaluated ZeBu over a one-week period, using existing design, and used it to co-simulate HDL testbenches, thereby reducing regression testing time. CISRA is now migrating HDL testbenches into C++ transactors with ZeBu.
Future Design Automation announced SystemCenter, which is a suite of co-development software tools for high-level software and hardware design and verification. The company says the new suite increases the productivity of DSP designers, algorithm developers, system architects, hardware designers, and verification engineers developing SoC that include complex algorithms. (Rhetorical question: Are there any SoCs that don't include complex algorithms?) Using the suite, system architects can take functionality created by software designers, create hardware architectures, and transfer the design to hardware designers for implementation in standard HDL environments. The company notes that all of these engineering disciplines can use the original C source code as a reference specification.
InnoLogic Systems, Inc. announced that Fujitsu used the company's ESP-CV functional verification offering to meet production delivery deadlines for Fujitsu's Mobile FCRAM (Fast Cycle RAM) burst mode devices.
Mentor Graphics Corp. announced what the company describes as a comprehensive FPGA design flow that “expands traditional FPGA tools with new technologies to address emerging challenges of complex FPGA designs.” The three-part flow extends from high-level FPGA design through PCB design, and includes “existing and future technologies” for the design and verification of the FPGAs, embedded systems, and PCBs containing FPGAs. Walden C. Rhines, Chairman and CEO of Mentor Graphics, sounded the trumpets for “existing and future” battlefronts when he said, “We're advancing our position in FPGA design by building beachheads around our tools that are de facto standards in their respective markets.” Meanwhile, the company says it will continue to deliver new tools and enhancements to existing tools that address FPGA design/verification, embedded systems design/verification, and PCB system design/verification.
Meanwhile - Mentor Graphics Corp. and Royal Philips Electronics announced a technology collaboration to help their mutual customers implement high-speed USB in embedded applications. The two companies says they are working jointly to create USB 2.0-compliant combinations of transceivers and IP, in the hopes that “proven interoperability will help customers by reducing risk, shortening development times, and lowering overall system development costs.” To date, Philips has used the Mentor Graphics USB IP reference platform to achieve compliance certification of the Philips UTMI Transceiver, ISP1503.
Finally - Magma announced that Goyatek Technology Inc. has implemented the first 0.13-micron SoC design in the greater China region using Blast Fusion and Blast Noise.
Model Technology, which is a Mentor Graphics company, announced the availability of its HDL simulator, ModelSim for Linux, running on Intel Itanium 2-based platforms. Mentor says it is the first EDA company to support the 64-bit Intel processor. Engineers from Intel and Model Technology report that they worked together to ensure “optimal performance while preserving the unique advantages of the ModelSim product.” Guru Bhatia, Director of IT Engineering Computing at Intel, said, “We are excited to see the ModelSim software product line from Model Technology on Intel Itanium 2 processor-based systems, offering the best-in-class 64-bit computing performance. This [tool] offering reinforces that the Itanium 2 processor is a feature-rich, stable, and easy-to-use high-performance 64-bit computing platform for developing and running mission-critical CAD applications for silicon design.” It'll probably do the trick, as well, if the application is just important, but not quite mission critical.
MIPS Technologies, Inc. announced that Wintegra Inc. has introduced two new additions to its 64-bit MIPS64 5Kc-based range of products for DSLAM systems. The WIN717D4 and WIN717D6 are designed to meet price, features, and performance requirements in small DSLAMs (24-48 ports), and are subsets of the WIN737. Additionally the two news products come with a range of communication protocols that are “royalty free and production verified.”
OEA International, Inc. announced a major update to its SPIRAL 3D-inductor design toolset for synthesizing embedded spiral inductors in analog and RF chips, hybrids, MCMs, and PCBs. The toolset can be used in batch mode, as a stand-alone UNIX GUI, or from within the Cadence DFII environment. If SPIRAL is used from within the Cadence framework, it automatically generates layout, schematic, and symbol views. New SPIRAL features include refined substrate modeling capability, support for various numbers of parallel metal layers in the winding or cross-under, and automatic generation of patterned ground shields.
RF Engines Ltd. announced the company has added high-speed polyphase DFT (Discrete Fourier Transform) cores to its DSP technologies IP. The company says these are the world's first polyphase DFT cores to be available as standard licensable IP that are fully characterized and ready to use off the shelf.
Sagantec announced Anaconda, which the company calls “a schematic-driven, constraint-based compaction tool that accelerates analog physical design by automating repetitive manual layout tasks and enabling analog design reuse.” Specifically, the tool intends to replace the manual effort required to correctly place and size the layout details of derivatives and variations for a given physical topology. Anaconda is described as a “correct-by-construction” tool, which reads sizes and constraints from a schematic and then refines the topology to automatically implement the specifications, checking symmetry, wire widths, matching, alignment, and correct design rules. Anaconda is integrated with Cadence's Virtuoso XL design system.
Silicon Canvas, Inc. (SCI) announced that KeyEye Communications has selected Silicon Canvas Laker for its KX5002 (and future) communication chip designs. The company says it will use Laker for creating analog blocks, chip assembly, and post-place-and-route DRC violations location and repair. KeyEye has established a production design flow with Laker, which has allowed the company to add advanced automation capabilities to the process.
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