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Industry News - Tools & IP

Applied Wave Research, Inc. (AWR) announced the Analog Office design suite, which the company says is targeted at “next generation analog and radio frequency integrated circuit (RFIC) designs, focused on total RF closure.” The company also says this is the first complete IC design system introduced in over a decade that is “specifically architected and optimized for analog and RFIC designs,” and that the design suite is integrated into existing digital and mixed-signal IC design flows.

AWR is taking on several large industry players with this introduction and says in the Press Release, “Analog Office software is an RF-aware design methodology built around the Intelligent Net (iNet) technology. Unlike existing 'net' constructs built on a 'digital-centric' data model, iNet technology is an RF-accurate net model addressing multiple levels of abstraction, including an ideal 'short-circuit' model, a lumped element model, a fully distributed transmission line, and a full 3D EM model. iNet technology provides concurrent and real-time connectivity information between the schematic and layout representations, and eliminates the need for a serial post-layout connectivity extraction step. Full control of simulation and analysis can be applied to iNet technology, in the same manner as is applied to all other devices in the design for complete RF design closure. Then the Analog Office system addresses high-frequency impairments that force the need to obtain complete 'RF closure' between the RFIC's system and circuit, electrical and physical, and design and test activities before commitment to IC implementation.”

Aldec, Inc. announced that its Active-HDL version 6.1 now supports C synthesis through its interface with Celoxica's DK2 Design Suite. The companies say that by adding support for Celoxica's C-based FPGA synthesis tool, system designers are now able to support VHDL, Verilog, C/C++, and Celoxica's Handel-C from a common, unified environment. Designers can use Active-HDL's design entry environment to develop code, and then invoke both HDL and C synthesis tools directly from its Design Flow Manager.

Also from Aldec - The company announced that Amirix Systems Inc.'s recent embedded design with 6+ million FPGA gates was accelerated over 16x using Aldec's hardware acceleration product, Riviera-IPT. While developing the design, Amirix says it previously simulated the design for three days in regression testing to confirm system-level functionality, but condensed verification time from three days to less than five hours using Riviera-IPT.

And this from Aldec, as well - The company announced that PnpNetwork Technologies, Inc. completed an ASIC core chip for a terrestrial reception set-top-box using Riviera-IPT to accelerate verification runs. The performance increase from “days to hours during project development” was primarily realized during the RTL debug stage, according to the companies where many of the design's small iterations previously created bottlenecks for simulation times.

Altium Ltd. announced the release of a new TASKING embedded software development toolset for the TriCore architecture that includes next-generation Viper compiler technology. Altium reports that internal benchmarking has shown increases in execution speed and decreases in code size of an average of 10%, compared to the previous TASKING TriCore toolset. The company also says, “The new toolset excels in performance of generated code, completeness of features, architecture support, and compliance with industry standards. The new toolset has been extensively tested to ensure compatibility with all leading third-party TriCore products.”

Ansoft Corp. announced that it has upgraded its Maxwell Equivalent Circuit Extractor (ECE), which will allow users to extract lumped parameter circuit models directly from Maxwell to SIMPLORER. The company says new ECE features include mechanical pins used for linear and rotational models, rotational models that can use either angle or speed, the ability to edit coil resistance and turns in SIMPLORER, and the ability to assign extra ports to physical domains.

ARC International announced that Altek has licensed an integrated development platform for use in product development, including the ARCtangent processor, the MetaWare Software Development Tool Suite, and the MQX/RTOS.

Atrenta Inc. introduced SpyGlass LP to optimize designs for low power by allowing users to create “power-efficient RTL” early in the design cycle, and eliminate many iterations now required to optimize for power consumption later in the design cycle. The product provides guidance for low power techniques targeting dynamic power, leakage power, and voltage management issues. MIT's EECS Professor Anantha Chandrakasan, said, “In order to get power efficient designs, low-power techniques need to be incorporated from the beginning. The quality of RTL code is very important for downstream optimizations targeting lower power designs. Atrenta's predictive analysis techniques can help create power efficient RTL and enable designers to deploy their low power design methodology."

Cadence Design Systems, Inc. and AsusTeK Computer Inc. announced that AsusTeK has selected the Cadence SPECCTRAQuest design and analysis product for its ultra-high-frequency, high-speed PCB motherboard designs. AsusTeK says its design team used SPECCTRAQuest for PCB development for simulation analysis and constraint-driven layout, provided that thorough solution-space analysis has been performed.

Also from Cadence - The company announced the release of the Cadence Virtuoso Chip Editor chip finisher, which uses the OpenAccess API and database to directly link the Cadence Encounter digital platform with the Cadence custom environment, a development which the company says provides customers with upwards of 10x performance and 3x capacity for digital and mixed-signal designs. Chip finishing is the final stage of design implementation and has traditionally required the exchange of multi-gigabyte data files (for example, DEF or GDSII formats) between digital and custom environments - a slow process. The new Virtuoso Chip Editor uses the OpenAccess database to eliminate the file-transfer bottleneck.

From Cadence, as well - The company announced that several additional companies, including ARM and NVIDIA Corp., have selected the Cadence Incisive verification platform for nanometer-scale IC development. The company says the new platform provides up to 100x more “full-chip performance” than RTL simulation, and that seven companies chose the platform in the first quarter of availability.

Finally - Cadence Design Systems, Inc. and MatrixOne, Inc. announced a strategic alliance to produce a “suite of product lifecycle management (PLM) solutions.” As part of the alliance, technologies from both companies will be combined to create “new collaborative design, component supplier management, and design-for-supply-chain solutions.” Cadence says that technologies acquired from SpinCircuit and the Thales Group will be integrated with design data management, change management, and collaboration technologies from MatrixOne to create products that will integrate with Cadence's electronic design products and MatrixOne's enterprise PLM offerings. Both companies says the their new offerings will support open integration with a wide range of third-party tools.

Meanwhile, in closely related news - Cadence Design Systems, Inc., MatrixOne, Inc., and IBM announced during a joint May 21st webcast that they are teaming together to deliver a “comprehensive, integrated set of PLM solutions for the global electronics industry.”

Dave DeMaria, Executive Vice President of Cadence Systems Solutions, said that this type of offering has never existed in the electronic market before, although he acknowledged that it's a very well known strategy in the mechanical world. Whether you agree that this type of offering is new or unique, Cadence believes “this new class of problems associated with collaborative design” will be solved by application of the integrated offerings from the three companies.

Specifically, the Press Release said, “The new offerings will combine business transformation consulting, application customization, installation, and training from IBM Global Services; platforms and software - including IBM WebSphere and DB2 middleware products; along with new, integrated PLM offerings from Cadence and MatrixOne (mentioned previously). This advanced solution will enable collaborative design directly from the engineering desktop, synchronize activities across the software, electronics and mechanical design disciplines, and make it easier for original equipment manufacturers (OEMs), semiconductor companies and Electronic Manufacturing Services (EMS) providers to work together.”

Not surprisingly, as part of this plan, Cadence, MatrixOne and IBM Global Services are “working with customers, other vendors, and industry groups to develop and support new standards to improve integration and interoperability across the key technologies used in the software, electronic and mechanical design disciplines.”

Meanwhile, most of us weren't waiting for Cadence, IBM, and MatrixOne to tell us that the semiconductor industry is no longer vertically integrated -and it's simply not plausible that Cadence, IBM, and MatrixOne have now just spotted the problems that arise from disaggregation in the market. But nonetheless, by throwing their core competencies at the problems in this carefully choreographed manner, the three companies may have hit on something here. The long list of advantages enumerated during the joint webcast include:

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