Movers and Shakers
Finally from Cadence - The company announced that it is expanding into mixed-signal designs with the enhanced Cadence UltraSim Fast-SPICE simulator. Cadence says it chose memory design as its first target application because of its extreme speed and capacity requirements. UltraSim's new capabilities include RC reduction and extraction-independent hierarchical stitching.
CAST, Inc. announced two new cores that are 100% software compatible with the M68HC05 and M68HC11 microcontroller families from Motorola. Cast says the cores are suitable for a variety of embedded controller applications and provide better performance than the originals. The company also says that both cores have been verified through core and system simulation, code coverage evaluation, and field testing of implemented products. They are available in soft format (HDL source) for ASICs or firm (optimized netlists) for FPGAs, and have been used in several ASICs to date.
Concept Engineering and Prover Technology announced an OEM agreement that gives Prover Technology the right to use Concept's Nlview Widget in the Prover eCheck equivalence checker. Nlview is a visualization engine, which the companies say will allow Prover to provide debugging features related to equivalence checking without implementing another schematic visualization engine.
Also from Concept - The company announced that its SpiceVison PRO visualization tool has been integrated with the CRITIC and HANEX digital circuit analysis software from Nassda Corp. Nassda announced it will sell a version of SpiceVision PRO directly to its customers under the terms of a comprehensive OEM agreement. SpiceVision PRO is designed to aid designers of high-performance digital circuits visualize critical paths and clock networks analyzed by Nassda software. The visualization technology demonstrates to designers the impact of their design decisions on the timing behavior of critical paths.
Denali Software, Inc. and Open Core Protocol International Partnership (OCP-IP) announced the availability of OCP-compliant Databahn memory controller cores. Denali and OCP say these compliant cores allow designers to integrate Databahn cores with other third-party IP using the OCP standard, and that “the new cores provide a highly configurable, OCP-compliant solution that promotes design re-use without re-work.”
Icinergy Software Co. announced release 4.0 of its front-end physical design exploration technology. The company says the new release introduces “proven” flows into Synopsys and Cadence physical synthesis and gate-level virtual prototyping tools, and includes new IP library management capabilities. Other new features in the release allow designers to model rectilinear blocks while still in the conceptual stage of the design, which the company says increases correlation between the early physical model and implementation in back-end flows. Additionally, 4.0 includes integrated library browsing and die-size estimation capabilities. Designers can select the required quantity of IP blocks from a repository, based on user-defined criteria. Then they can create reusable, technology-independent port definitions, and simplify creating standard interfaces and bus structures by applying the definitions to multiple blocks in a physical design.
Incentia Design Systems, Inc. announced today that it has improved the performance of its full-chip, gate-level Static Timing Analyzer (STA), TimeCraft, for multi-million gate, high-performance designs. The company says the new release improves runtime up to 5x and reduces memory utilization up to 30% on large designs, when compared to the previous release.
InTime Software, Inc. has introduced Time Director, a product for the electronic design desktop that the company says will enable “cost-effective rapid” timing closure and will accelerate existing methods by a factor of 40X to 50X. Time Director is a part of RTA, which predicts the RTL-to-GDSII flow, and moves static timing analysis to the front of the design process, operating at RTL.
Magma Design Automation Inc. and Alternative System Concepts (ASC) announced that Magma used the ASC ALF parser and API access routines to integrate Accellera's Advanced Library Format (ALF) standard into Magma's Blast Fusion physical design system. As a result, Magma was able to meet NEC Electronics America, Inc.'s requirement for Magma's IC implementation solution to support the standard.
The Press Release said, “As the industry advances from micron to nanometer-scale technology, previously disregarded characteristics have become dominant factors driving design decisions. NEC Electronics America recognized this change early and decided to put priority on modifying its tool flow to support ALF libraries with signal integrity and power characterization. To build ALF support into its Blast Fusion, Magma turned to ASC, which was the first to offer an ALF parser and API for easy integration into a variety of EDA tools.” It looks like lots can be accomplished when multiple entities are working together.
Also from Magma - The company announced that it will have access to ARM microprocessor IP and will develop a fully validated IP implementation flow using Blast Create, Blast Fusion and Blast Noise products. The two companies say they will work together implementing the cores in widely used process technologies. The documented flow including scripts and design guidelines will be published by Magma in the third quarter of 2003.
Monterey Design Systems announced that the Monterey design planner has been qualified for inclusion in IBM's Blue Logic standard ASIC design methodology. The design planner starts the silicon virtual prototyping process by automatically placing the large macros. The resulting floorplan continues through the IBM Blue Logic methodology until the final physical implementation is complete. Qualification work for Monterey's prototyper (Sonar) is also in process. IBM conducted an evaluation of the Monterey products using a test chip containing 1.5 million gates and 200+ large macrocells built on IBM's 130-nanometer process technology. The companies reported that the chip-level design plan was completed in less than an hour. The design planner was used in the process to automatically place all of the blocks and optimize the hierarchy for final implementation. The Monterey design planner will be made available to all IBM Microelectronics ASIC design centers and their customers.
Also from Monterey - The company announced that STMicroelectronics taped out two production 130-nanometer SoC designs totaling 9 million gates using the company's Progressive Refinement technology. The Monterey tool suite includes hierarchical design planning, physical synthesis and prototyping, and final physical implementation. The larger of the two ST designs was an integrated single-chip set-top box solution with over eight million gates, 3.2 megabits of SRAM, 70+ large macro blocks including both a 64-bit and a 32-bit CPU core, embedded analog macros, multiple clock domains running off a 200MHz chip-level clock, and 400 I/Os. ST says that on the second design, die size was critical and Progressive Refinement provided early feedback to the RTL designers to produce a netlist optimized for density.
Novas Software, Inc. announced technology enhancements to the core debug platform for the company's Debussy Debug System and Verdi Behavior-Based Debug System. The company says these enhancements include database upgrades that use less memory and double the performance of many debug operations. The enhanced infrastructure also integrates new clock tree and timing debug features, and supports the production release of Novas' assertion-driven debug capabilities.
Also from Novas - The company has announced product support for SystemVerilog, the Accellera standard based on the Verilog hardware description language (HDL). The company says designers using SystemVerilog will be able to “leverage the advanced tracing and analysis capabilities of Novas debug systems to quickly locate, isolate and understand the root causes of design errors.”
Sequence Design announced a joint development effort with Toshiba Corp. to optimize power and “reduce wasted power consumption” in semiconductors, based on Toshiba's MTCMOS (Multi-Threshold CMOS) technology. Takashi Yoshimori, System LSI Division Technical Executive at Toshiba Semiconductor, said, “It is now common for 20 percent or more of a chip's power budget to be consumed by leakage power alone, severely limiting the designer's ability to maximize circuit efficiency and performance. Sequence's leakage power methodology provides us with a way to turn the power supply to logic on and off as needed, eliminating waste and greatly extending battery life for handheld products.
Vic Kulkarni, President and CEO of Sequence, said, “We are honored to have the opportunity to partner with Toshiba to address the industry's growing concern about low power design. As Dr. Gordon Moore noted at this year's ISSCC conference, leakage power is a trend that is spiraling out of control. By working in concert with the most advanced design and process-science talent, we can be assured that our joint breakthrough on leakage power will be well suited to the challenge of power consumption at the nanometer level.”
Be the first to review this article