EDA, Inc.


The 5 of them seized the opportunity to drive home their point.

“EDA is full of really smart people.”

“The tools are evolving and getting better.”

“The industry is committed to moving forward.”

“EDA wouldn't be fun if all of the challenges were solved.”

I told them that their persistent message of optimism about EDA and the way it is structured for innovation, etc. was something good. I told them that they should take their show on the road.

Roethig said, “Yeah, we could do that. We could have a panel discussion and you could moderate it.”

I said, “I think I just did.”

We all shook hands and went our separate ways.

I rode one of the many long, thin escalators down to the first floor to get my morning mocha. As I glided down alongside the 5-story windows that define the west wall of the building, I looked out over the many tall palm trees swaying slightly in the morning breeze. There are over a hundred of them – I counted – lining the paths and gardens between the Convention Center and the adjoining hotel complex.

I thought about how the palm fronds at the top touch each other in the breeze, from tree to tree, green and pleasing and free, to create an integrated canopy overlooking the patio below. I thought about the stern, rigid trunks that support that canopy. I was looking right at those trunks now, as the escalator reached the first floor.

Isn't there a corollary there, I thought. The pretty, appealing fronds way up high, all interacting with each other, partnering, and aligning, and re-aligning – making swishing noises in the wind. Aren't they just like the sales and marketing and management portions of EDA – the pretty and noisy portions.

But the sturdy, unbending trunks of the palms below – aren't those the engineers. Look how they think in straight and rational ways about how to conduct the water up to the fronds, how to withstand the stresses of wind and weather, how to extract and deliver nutrition to the system. The trunks are the problem solvers. They're there because they love the challenge of it all. They never fall down on the job. They don't look at all like the fronds. They don't swish and sway. And they're definitely not very pretty.

The palm fronds are pretty and fun and eye-catching. They make it all worthwhile by helping the trunks to focus on an end goal. But when the fronds tire, they wilt or drop. The trunks never do.

EDA is based on technology. It is based on science and engineering and rigorous research and development. Let's not forget, no matter how fun the party, how glib the marketing message, how choreographed the press conference, how clever the business partnering, the mergers, the acquisitions, the investments, the stock valuations – the trunks are the sturdy part of the garden.

The engineers continue to support the canopy because the problems continue to fascinate them and tax their intellectual abilities. They're having a wonderful time in a way the fronds will never understand. The fronds would be nothing without them. Absolutely nothing.



Industry news – EDA and IP

Agilent Technologies Inc. announced that Agere Systems selected the Agilent RFDE (radio frequency design environment) to develop Agere's RF/mixed signal IC design flow. The companies say the new design flow will allow Agere designers to model and simulate high-frequency effects in new chip designs with “greater speed, accuracy and efficiency.”

Analog Design Automation, Inc. (ADA) announced that the company has partnered with several layout vendors to integrate ADA's front-end optimization tools with a range of layout tools. The first announced partner vendors are CiHraNova, Sagantec, and Silicon Canvas. The company says that “the partnerships are designed to reduce the time spent on the analog portion of IC design by enabling designers to focus on the design process rather than interoperability issues. This will help ensure that customers are provided a consistent flow between ADA's Genius optimization tool suite and the customer's choice of layout partners.”

Ansoft Corp. has released the AnsoftLinks v2.5 interface for the Cadence Virtuoso digital and analog custom IC layout editor. The companies say the interface makes it possible to export circuit layout cells from within Virtuoso to Ansoft's EM analysis tools. Ansoft is a member of the Cadence Connections Program.

ARC International announced that iStor Networks licensed the ARCtangent-A4TM, user-customizable RISC processor plus software and development tools in the development of its iSNP8000 (IP storage network processor).

Cadence Design Systems, Inc. announced that Taiwan Semiconductor Manufacturing Company, Ltd. has adopted the Cadence Encounter digital IC design platform as a part of TSMC's new Reference Flow 4.0. The companies say this move is part of their collaborative efforts “to optimize the silicon design chain for mutual customers by addressing difficult nanometer design challenges, such as full-chip signal integrity closure.”

Chip Express, Inc. and Synplicity Inc. announced that Chip Express has endorsed Synplicity's Synplify ASIC software within its structured ASIC flow. Doug Bailey, Vice President of Marketing at Chip Express, said, “FPGA and ASIC design tools and methodologies have taken divergent paths. Designers are already familiar with Synplicity's Synplify software for FPGA design. With the customized version of our libraries for the Synplify ASIC software, designers can more easily tie together FPGA and ASIC designs and easily transition to structured arrays without learning to use different tools and platforms.” Interesting news on the heels of Synplicity's recent announcements with LSI Logic.

CoWare Inc. and Novas Software announced they are collaborating to deliver an “integration roadmap between their tools” and bring Novas' debug technology to SystemC. The companies will create a link between CoWare's ConvergenSC tools and Novas' Debussy debug system, which the companies say will allow designers to debug SystemC, Verilog, and VHDL in a common environment for SystemC and HDL flows.

Also from CoWare – The company announced that it will also work with Verisity to produce an integration roadmap for the companies' products. (See Verisity announcement below.)

Denali Software, Inc. announced that it is now offering configurable IP cores for PCI Express technology. The PCI Express core was developed and verified by IBM for use in its own ASICs, foundry, and standard product designs. Denali will directly sell and support application specific configurations of the core through its own channels along with its existing PureSpec verification IP product for PCI Express.

Golden Gate Technology Inc. announced GoPower to “completely address the long-neglected problem of low-power layout.” The tool contains a floorplanner, a power grid synthesis and automatic placer to permit a power-driving architectural approach to physical design. Oki Semiconductor endorsed results they've achieved through use of the tool.

Incentia Design Systems, Inc. announced performance improvements in TimeCraft, a static timing analyzer. The company says the new release “improves its runtime up to 5x and reduces memory utilization up to 30% on large designs, when compared to the previous release.”

iRoC Technologies announced the completion of a series of radiation tests at several neutron and proton facilities on SRAM, DRAM Flash, and TCAM memory types to measure soft error rates (SER). The company says that for 0.13-micron technologies and below, soft error rates for test die are necessary to verify the compliance with quality and reliability specifications.

Magma Design Automation Inc. announced the company has completed a comparative study of TSMC's libraries with six variations of the 0.13-micron process node with a “widely used embedded microprocessor core.” Magma worked with TSMC's Design Services Division to qualify timing, RC extractions, and DRC.

Monterey Design Systems announced the initial release of the Calypso silicon virtual prototyping (SVP) system. The company says Calypso is built on Monterey's progressive refinement technology, and that Calypso is the first SVP system to include both hierarchical design planning and physical prototyping in a single tool. The system combines hierarchical design planning, physical synthesis, and physical prototyping in a single tool built on top of a hierarchical database, to allow for optimizing the timing of a path that spans multiple blocks without having to go into each individual block and optimize each sub-path contained within the timing path. It also provides analysis so that if the power rail is widened at the chip-level, the tool can measure the effect on IR drop incrementally inside all of the blocks.

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