The Root of all Evil
But to be on the safe side, this is where I'll begin my next conversation with him. If my impression is correct, we can go on from there.
Industry news - Tools and IP
Agilent Technologies Inc. and Tiburon Design Automation Inc. announced an agreement to integrate Verilog-A modeling technology from Tiburon-DA into the Agilent RF Design Environment and Advanced Design System (ADS) software packages. The companies says that the addition of Tiburon's Verilog-A compiler technology will enable analog, RF, microwave, and mixed-signal system designers to use Agilent's simulation tools to develop “highly accurate” analog behavioral and compact device models that simulate at speeds comparable to C-based models.
Also from Agilent - The company introduced what it is calling “the industry's first built-in connected solution application for amplifier characterization,” the Agilent Connection Manager, which “simplifies the integration of Agilent hardware and Agilent ADS software.” The new amplifier characterization capability provides engineers with “measurement-based accuracy” for wireless designs and is intended to help speed simulation times by replacing amplifier circuit schematics with measurement-based behavioral models.
Analog Design Automation, Inc. (ADA) announced that, as a member of the Cadence Connections Program, it has integrated its front-end optimization tools into the Cadence layout design flow. The companies say that, through this integration, joint customers will be provided a “consistent design flow” between the Cadence layout environment and ADA's Genius optimization tool suite. Matthew Raggett, President and CEO of Analog Design Automation, said: “ADA is pleased to be able to leverage the Cadence Analog Design Environment with the most powerful optimization and performance tradeoff exploration tool set in the market.” (Editor's Note: Next to “orthogonal,” the word “leverage” is my 2nd most favorite word.)
Barcelona Design Inc. announced a “strategic partnership” with UMC aimed at developing synthesizable PLL and ADC “solutions” targeted at UMC's process technologies, including 0.18 micron, 0.15 micron and 0.13 micron. The companies say the partnership will result in a “collaborative effort to align product roadmaps based on customer needs,” and will enable UMC to “rapidly provide customized analog circuits to qualified customers using Barcelona's synthesis solutions.”
Cadence Design Systems, Inc. announced the Cadence 15.0 PCB and IC packaging design environment. The company says the release includes “enhancements and innovations spanning the entire integrated flow. Now, engineers have an integrated environment for designing and implementing gigabit serial interfaces in high-speed PCB systems through a simulation and constraint-driven differential interconnect implementation from die-to-die across all three system fabrics: silicon, IC Package, and PCB.”
According to the Press Release, additional advances include new capability for the automated design of stacked-die systems-in-packages (SiP), unified and automated library part creation, validation and management, environment, dynamic real-time copper pour, plow and editing, and advanced simulation capabilities for signal integrity model verification. Additionally, the release provides for the use of XML for data-driven symbol generation, management and portability, the capability to import pin and package data directly from internet-available datasheets in .PDF or .CSV formats, on-line part validation to user-definable company standards, and automatic library management routines that track changes between part versions, to provide reporting of revision differences.
Fintronic USA, Inc. announced the release of an API-based interface between Super FinSim and the Debussy Debug System from Novas Software, Inc. The company says the new interface provides more effective tool interoperability and simulation performance than the previous PLI-based mechanism. Dr. Alec Stanculescu, CEO and president of Fintronic USA, Inc., is quoted in the Press Release: “This new interface between Super FinSim and Debussy will provide our joint customers with a more effective solution for Verilog design verification.”
Hier Design Inc. has announced its first product, the PlanAhead hierarchical floorplanner, which the company calls “the heart of its silicon virtual prototyping solution for high-end FPGAs.”
The Press Release says, “The types of problems designers face when designing complex FPGAs include the inability to achieve performance requirements, unpredictable routing results, routing congestion, tightly packed designs, critical paths spanning hierarchy, or heavily constrained interconnect. Current EDA tools force designers to fix each problem individually and then re-implement the entire flattened design. The result is lengthy and [requires] numerous design iterations that, in turn, often lead to cost overruns, slipped schedules and missed market opportunities.”
“ASIC designers, however, have largely alleviated these problems through the widespread use of hierarchical floorplanning, a design step between synthesis and place and route, which reduces the number and length of design iterations. Like its ASIC counterpart, the PlanAhead floorplanner increases performance and reduces the number of design iterations by giving designers advanced insight into the place and route process.”
“PlanAhead provides a hierarchical, block-based and incremental design methodology, enabling designers to change only one part of the design and leave the rest intact, shortening design iterations. Changing smaller portions of the design also helps maintain performance requirements, since results of iterative place and route are often unpredictable, particularly when performed on flattened netlists of entire chips. Incremental design can improve physical design time by two to four times over flat methodologies.”
“PlanAhead provides manual or automatic partitioning, manual or automatic physical block sizing and placement, along with clock I/O and clock region planning. Designers can implement blocks individually and then assemble them in PlanAhead for analysis of the partial design's performance before other blocks have been completed, then make any necessary changes before proceeding. [The tool's] design analysis capabilities include timing, connectivity, utilization, I/Os, clock regions, and carry chains, with power and other analysis capabilities to be added in the near future, [as well as] integration with the Xilinx design flow by encapsulating place and route commands directly in the GUI. It supports block-based and area-based flows.”
All of this should be good news in the FPGA world. The proof, as they say, will be in the pudding.
HPL Technologies Inc. announced the TechXpress IP Solution. The company says TechXpress consists of a family of array technologies supplemented with analytical software, and that the IP is available for 0.35-micron to 65-nanometer process technologies.
The Press Release says “Technology development groups are today challenged with developing and bringing to market new processes. Product engineering groups face similar challenges to resolve yield issues during volume production. Historically, process and product engineers have relied on discrete test structures to characterize process behavior. At sub-130-nanometer technology nodes, it is no longer possible to utilize traditional methods of process characterization for the following reasons: thousands more parameters have to be measured, the resources required for designing additional test structures are not available to many customers; and the silicon real estate available to implement manufacturing monitoring test structures is shrinking.”
“TechXpress' innovative array technology affords users with orders of magnitude more test structures within limited silicon area and pads. Using TechXpress IP, customers are able to generate a significant number of statistically relevant electrical responses to characterize the most advanced process technologies. Integrated analysis software specifically tailored to the IP enables rapid identification of the root cause of failures leading to faster yield improvement.”
Mentor Graphics Corp. announced the availability of the new Capital Logic software tool for the design of electrical wire harness systems. The company says Capital Logic is the latest addition to the Mentor Graphics Capital Harness Systems data-centric design flow announced in February 2002, and automates the generation of schematics. Mentor also says that, in contrast to file-based systems commonly used for wire harness design, the Capital Logic tool addresses “complex data management requirements via the inclusion of Capital Manager, a relational database and ECAD data management system that is the foundation to all new CHS tools. The Capital Logic tool is also the first CHS application to employ a new Mentor Graphics view synthesis technology which greatly enhances design reuse and overall productivity by generating graphical views directly from underlying data.”
Also from Mentor Graphics - The company announced that Faraday Technology has selected the Mentor Graphics Calibre xRC product as its transistor level and GDSII-based gate level parasitic extraction tool for SoC designs.
True Circuits, Inc. announced the immediate availability of a line of spread-spectrum and low-bandwidth PLL analog hard macros with the company's LockNow! Technology. The Press Release says, “The low-jitter Spread Spectrum PLL allows the spread-spectrum functionality to be included in the ASIC rather than requiring a separate part on the system board, thus reducing manufacturing costs. It is designed to multiply an input clock by an integer or fixed-point number with a frequency spreading capability suitable for PC, networking and consumer electronics applications that require spread-spectrum clock sources to satisfy FCC requirements for RF emissions. The Low Bandwidth PLL is designed to address the problem of excessive jitter from system clocks originating from lower-quality crystals. This PLL design generates high-speed clocks required for processors and chip interfaces that require low-jitter performance.”
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