More on Object-Oriented Design

I use a compiler by a small company in Wisconsin, running on a decade old 486 PC with DOS, which does most compilations in a couple of seconds or less. That supports the slow downs due to MTOS. It is certainly cheaper than 6-figure EDA tools running on expensive workstations under UNIX or Windows.

Alas, it is not possible to find a group of IC designers willing to look into something that is old and lacking in glamour, [even if it is] much simpler and more efficient. The Ada I use is a small subset restricted according to an Annex in the ISO standard for safety and security, while 40 of the 46 retained keywords are also in VHDL's 96 keywords.

Now consider this. What if China picks up the Ada approach? What if the Chinese design community uses common sense due to economic necessity to avoid using costly EDA tools? Vast numbers of lower paid designers, not relying on costly EDA tools, would be able to design ICs more efficiently. That, coupled with cheap foundries, would mean that even more design jobs in the U.S would be displaced. Fortunately for American designers, China has the copy-America syndrome. China followed the U.S. in adopting Ada, and then followed the U.S. in abandoning Ada.

My message is this - Using Ada for IC design is not high tech, it's just common sense. Designers would not have to rely on costly EDA tools and would be able to design ICs more efficiently.


Dr. Sy Wong

(Editor's Note - Dr. Wong's well-known advocacy for Ada has appeared in many venues over the years.)

Industry news - Tools and IP

Agilent Technologies Inc. announced that the Shanghai Research Center for Integrated Circuit Design (ICC) has selected multiple Agilent automated test platforms, including the Agilent 93000 SOC Series and the Versatest Series for memory testing. ICC says it selected the testers to address increasingly complex and sophisticated test needs for China-based IC design houses and manufacturers in the greater Shanghai area.

Per the Agilent Press Release: "The IC industry is one of the Chinese government's key economic development projects. ICC, the first IC design industrialization center in China, supports this mission by providing design and testing resources to local semiconductor companies. The resources, including shared EDA software, multi-project wafer (MPW) projects, and sophisticated testing services, enable dozens of IC design houses in Shanghai to achieve faster time to market for their products. ICC is recognized as more than the specialized technology innovation and industrialization center for IC design houses: it is also considered the information communication and technology cooperation center for the whole IC industry in Shanghai."

Also from Agilent - The company announced that Infineon Technologies has selected the Agilent 93000 SOC test system to test the company's advanced semiconductor devices for high-speed wired communication applications.

Related to Agilent - United Monolithic Semiconductors (UMS) announced the availability of a new release of all its Design Kits that adds "significant new functionality" and targets the latest version of Agilent Technologies Advanced Design System - ADS 2003A. During the Early Access Program, UMS says it has worked in close relationship with Agilent to qualify this new release and to support its new functionality.

Artisan Components, Inc. announced that Teradiant Networks used Artisan's analog, mixed-signal, and digital IP in the development of a new high-performance configurable network-processing chipset. The TeraPacket chipset comprises a multi-service packet-processing engine and a multi-service traffic manager in versions for 10Gbps, 20Gbps, and 40Gbps performance needs. Teradiant says it used Artisan's specialty I/Os, standard cell library, high-speed memories, and high-performance 533MHz PLL in TSMC's 0.13-micron process.

Also from Artisan - In late July, the company announced the availability of its physical IP products for IBM's 0.18- and 0.13-micron CMOS foundry technologies. The company says these products are available at no charge to licensed customers under the Artisan Foundry Library Program. Additionally, the company announced that NVIDIA Corp. has adopted Artisan's design platform, including its memory products, for NVIDIA's 130- and 90-nanometer designs.

Cadence Design Systems, Inc. announced that Aspex Technology selected Cadence tools to help develop "scalable, fully software-programmable processors that deliver high performance with low power consumption." Aspex says it will "deploy" Cadence products under a two-year agreement covering every element of its design flow, from initial design to simulation and verification.

Cimmetry Systems announced that AutoVue 17.1 has been released, and that the new releases includes significant new features and a host of new format supports for tools from Mentor, Cadence, Zuken, and others.

Emulation and Verification Engineering (EVE) released ZeBu-IP, a companion version of its hardware verification system known as ZeBu (Zero Bugs). The company says the new product is configured to support IP-based design methodologies. The Press Release says that "The designer can still enjoy the speed of emulation with the accuracy of an actual hardware representation of the design and the interoperability made possible by supporting the most complete hardware and software verification environment."

Icinergy Software Co. announced that it is shipping release 4.0 of its pre-synthesis physical design exploration technology. The company says the release introduces new capabilities in three product configurations that address design flow and market-specific needs for early physical planning of SoC products and complex ASICs.

Per the Press Release: "SoC Preview is a desktop physical design exploration tool that allows ASIC vendors to conduct on-site die size estimation, power planning and part quoting during initial meetings with potential customers. Among many key functions, SoC Preview can quickly generate PDF datasheets that allow side-by-side comparison of alternative combinations of IP blocks, macros and process technologies. SoC Plan encompasses hierarchical design planning capabilities and HDL entry (Verilog/VHDL) for physical architectural-level planning, and for IP evaluation, selection and integration. SoC Plan includes advanced automatic and interactive floorplanning, IO placement and interconnect planning capabilities, and it facilitates continuous design analysis and refinement to ensure that designs meet their physical constraints. SoC Prototype adds timing-driven block placement and automatic synthesis constraint generation capabilities that guide the synthesis and gate-level handoff processes. An integral hierarchical timing budgeting algorithm extracts path information from the tool's ultra-fast virtual router to create realistic synthesis constraints that reflect delay through trial routes." The company says that users of Icinergy's SOCarchitect product will receive a no-cost upgrade to the new SoC Prototype product.

Nassda Corp. announced that TransChip Inc. has adopted Nassda's HSIM hierarchical circuit simulator and analysis tool for verifying TransChip's CMOS imager-based camera-on-a-chip designs. Per the Press Release, Tiberiu Galambos, Analog Design Manager at TransChip, said "Before HSIM, we were using a hierarchical approach with Verilog-A models, which did not permit us to run transistor-level simulations at higher levels of hierarchy that would involve many tens of thousands of devices. With HSIM, we were able to run detailed transistor-level simulations of the complete interface of the digital control and the full-custom analog imager."

Synchronicity and Royal Philips Electronics announced the successful implementation of a new semiconductor IP delivery, management, and support system built with the Synchronicity Publisher Suite. The companies say that the IP Yellow Pages constitutes a key element in Philips' semiconductor reuse infrastructure. It hosts to date 400+ IP cores from 20+ internal and external IP providers. The IP Yellow Pages is a design resource portal within Philips for exchanging IP amongst both internal and external sources.

The Press Release says, "Fine-grained access control and robust SSL encryption ensure the security of these valuable design assets, while usage tracking and audit trails guide IP investment decisions. Design blocks in the IP Yellow Pages are graded for quality and labeled with a color code, to help engineers make the best risk/reward decisions. To accelerate the selection and use of IP blocks, the system also holds associated overviews, datasheets, specifications, models, and test files. Thanks to a link to an in-house IP configuration engine, design teams can configure and download their IP through IP Yellow Pages. Whereas most IP in the system is freely accessible to all users, download access to restricted designs (e.g. priced IP from external sources) is controlled through a user request system. Through a dedicated IP Yellow Pages extranet implementation, Philips' customers involved in co-development projects can also enjoy immediate access to the IP repository."

I had a chance to speak to Paul Gibson, Vice President of European Operations for Synchronicity, on August 6th. He was en route to a meeting in Portsmouth, U.K., speaking from his car on a cell phone, while I was on a landline in Silicon Valley. You've got to love technology.

Per Gibson, "It's four and a half years since our first agreement with Philips, and now we have 1200 seats across the Philips [organization]. We've helped Philips in many ways - with multi-site collaborative design development, with integrating with other companies that Philips has merged with, and with bringing teams together from completely different companies [partnering with Philips]. And we've entered into a 6-phase process with Philips to develop an enterprise-wide reuse environment."

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