Two sides to every story

InTime Software, Inc. announced that Sony Corp. of Tokyo has adopted InTime's Time Planner for use in its SoC flow. Per the Press Release, Sony chose InTime because of its “unique RTL Timing Analysis software that provides fast and accurate RTL timing analysis and RTL floorplanning. Time Planner supports Sony's RTL handoff flow by providing accurate timing information on the RTL code before handing it off to the chip implementation flow.” Bob Smith, InTime's President and CEO, is quoted in the same Press Release: “Sony has been instrumental in helping prove out the value of using RTL timing analysis in a production flow. It is becoming clear that RTL timing analysis will play an increasingly important role in the evolving IC design flow.”

Magma Design Automation Inc. announced that Toshiba Corp. and Toshiba Microelectronics used Magma software to successfully tape out and achieve first-pass silicon success on a 2.5-million-gate, low voltage (under 1.2V), low-power and high-speed consumer application device. The companies report that the complex SoC had 100+ clocks, including some running faster than 200 MHz. The chip was implemented utilizing Toshiba's TC280 (0.13-micron technology node) process and “Magma's integrated physical, hierarchical and signal integrity design technology.” The SoC included various operating modes, IP including ROM, RAM, and tricky interfaces, yet according to the companies was implemented in just four weeks using the Magma tools.

Also from Magma - The company announced that Applied Micro Circuits Corp. (AMCC) taped out a 622 MHz design with 3.4 million “placeable objects” using Blast Fusion, Blast Noise, Blast Plan, and Blast Rail. The company also reports it received AMCC's "Supplier of the Year" and "Innovation Award" commendations for “helping AMCC bring products to market in a timely and cost-effective manner.”

Mentor Graphics Corp. and Verisity Ltd. announced a technology collaboration that will allow customers to test Mentor Graphics Inventra IP functionality and help ensure smooth integration of an IP core into a target design. Mentor Graphics says it is joining Verisity's Pure IP program and can now deliver verification toolkits based on Verisity's Specman Elite automated functional verification methodology for its IP. The verification toolkit includes executable checkers and coverage scenarios that ensure correct IP integration. The toolkits act as an invisible wrapper around the IP, allowing customers to automatically check for adherence to the rules and flag incorrect usage as well as measure the coverage of the IP interface.

Michael Kaskowitz, General Manager of Mentor's IP Division, said: “Customers are pushing for sophisticated verification components that ease the dual problems of performing comprehensive functional validation of an IP block and also providing capabilities to migrate to pre-silicon, SoC, system-level testing. The Pure IP program will help us deliver flexible verification toolkits to our customers."

Also from Mentor - The company announced design-for-test (DFT) support for the AMD Opteron processor and AMD64 architecture. Mentor says it will offer AMD64 versions of its embedded deterministic test (EDT) tool, TestKompress, and its automatic test pattern generation (ATPG) tool suite. Robert Hum, Vice President and General Manager of the Design Verification and Test Division at Mentor, is quoted in the Press Release: “Our DFT products have been available on Linux for some time and we planned our 64-bit rollout to coincide with the growing industry need. The flexibility and scalability of the AMD64 architecture complements the flexibility and scalability of our tools and offers customers a comprehensive solution for their next generation designs."

One last item from Mentor - The company announced that it has selected Paradigm Works to aid in the development of system-level verification toolkits that Mentor will deliver with its Inventra IP. Paradigm Works says it offers an advanced verification component technology that ensures that customers can rapidly integrate their devices based on Mentor cores and thoroughly validate the quality of the integration.

Per the Press Release, verification is one of the most critical parts of the SoC development process. With ever-increasing mask costs, it is critically important to be assured that a design is functional before tape-out. The semiconductor industry is moving to the use of sophisticated verification components to facilitate SoC functional verification - especially as typical designs now carry multiple interfaces using different complex, communication protocols. This presents a challenge to designers, as verification environments must move vertically from the IP level to the chip level, so that the interaction between all sub-systems can be verified to a high degree of confidence.

Dave Wood, Director of Marketing for the IP division of Mentor Graphics, is quoted: “Increasing IP complexity requires a layered approach to verification to provide SoC designers with early feedback on potential system-level problems. Paradigm Works helps Mentor Graphics extend verification to the system level by providing a feature rich verification component to improve the functional quality of our customers' designs, and help achieve first pass success.”

MLDesign Technologies today announced the availability of a new MLDesigner evaluation CDROM that can be used with Windows computers. The new CDROM temporarily installs a temporary Linux operating system on a Windows computer and then loads MLDesigner for use. While in operation, MLDesigner accesses Linux files from the CDROM. After the evaluation, MLDesigner and all Linux files are removed from the host computer. Currently, MLDesigner runs on Solaris and Linux; a Windows version is in development. The evaluation CD contains a complete functional version of MLDesigner, including Discrete Event, Data Flow and Continuous Time design domains, a library of 2000+ design blocks, 400 demonstration systems, and documentation.

Synopsys, Inc. announced that Agere Systems used Synopsys' Galaxy Design Platform, including Physical Compiler, Astro, Star-RCXT, and Jupiter to tape out the 5G APP550 network processor in a 0.13-micron process. Agere says its ASIC design flow is built around Physical Compiler and that company engineers used Physical Compiler's synthesis and placement together to obtain a “timing-clean result in a short and predictable time.” The APP550 network processor was designed using Agere's SoC design flow, which centers on Astro for physical implementation. The companies say that the tight integration between Physical Compiler and Astro's signal integrity-aware routing allowed Agere to complete the network processor on-schedule and produce parts working to specification.

Also from Synopsys - The company announced that NEC Electronics Corp. has adopted Star-RCXT for its 90-nanometer CB-90 design flow. NEC and Synopsys say the companies collaborated to improve Star-RCXT's advanced interconnection modeling technology for CB-90's fine copper process features, which includes spacing, width and metal density-dependent wire resistance and capacitance calculation. The companies also say that Star-RCXT's support for advanced copper features “enables NEC Electronics to meet timing and signal integrity sign-off accuracy goals for designs using their 90-nanometer process.” Meanwhile, NEC says it Electronics' CB-90 ASIC design platform utilizes “its most advanced system LSI process technology, supporting clock speeds up to 1 GHz and featuring up to 100 million usable gates.” That's a helluva lot of gates.

Synplicity Inc. announced its FPGA logic synthesis and physical synthesis products now provide support for the Xilinx Integrated Software Environment 6.1i (ISE). The companies say that Synplicity's Synplify and Synplify Pro FPGA synthesis software can work directly with Xilinx's ISE 6.1i software. The Press Release says, ”Customers using Synplicity's Synplify logic synthesis and Amplify FPGA physical synthesis products together with ISE 6.1i will have access to a complete FPGA design solution for their high-speed designs.”

Not surprisingly, both companies feel the announcement to be mutually beneficial. Jeff Garrison, Director of FPGA products at Synplicity is quoted: “Leading edge devices like Spartan-3 and Virtex-II Pro from Xilinx have opened up significant new opportunities in electronic applications for programmable logic. These applications require advanced design software like Synplify Pro, Amplify and ISE 6.1i to get the most out of the silicon.”

Steve Lass, Director of Software Product Marketing at Xilinx is quoted: “Through our continued partnership [with Synplicity], we are providing designers with comprehensive design flows from synthesis to place and route. These design solutions, coupled with Xilinx's flagship Virtex-II Pro Platform and 90nm/300 mm Spartan-3 low-cost FPGAs, create the highest performance, most cost-effective hardware/software solution available in logic design today.”

Similarly - Mentor Graphics Corp. announced a collaboration with Xilinx, Inc. to provide “seamless operation between its FPGA Advantage design environment and Xilinx's recently announced Integrated Software Environment 6.1i (ISE).”

The companies say that FPGA Advantage, integrated with Xilinx's new ISE 6.1i tools, delivers a complete FPGA flow that redefines the standard for productivity in programmable logic design software. Both Mentor and Xilinx say they “are committed to providing the most complete, intuitive design solution available for FPGA design.”

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