What Goes Around Comes Around
Likewise, Synopsys, Inc. and Artisan Components, Inc. announced a collaboration to develop a hardware platform that validates the interoperability of their PCI Express IP solutions. The companies say the platform conforms to the PIPE (PHY Interface for PCI Express) standard, and that they plan to develop a mother/daughterboard platform utilizing Synopsys' DesignWare PCI Express Endpoint Controller Core and Artisan's PCI Express PHY IP. Synopsys and Artisan plan to present the offering in the fourth quarter of 2003.
Per the Press Release: “The platform demonstration will consist of two boards: a Synopsys-developed motherboard including FPGAs to house the Synopsys Endpoint Controller with driver software, and a daughterboard consisting of Artisan's PHY silicon. The interface between the two boards will adhere to PIPE specifications. Synopsys' motherboard will include three critical protocol layers - the logical PHY layer, the data link layer and the transaction layer. Artisan's daughterboard will include a complete serial link including mux/demux, 8b/10b encode/decode, elastic buffer and clock recovery circuitry that will be compliant with the PCI Express Base 1.0a Specification. Testability features for the Artisan daughterboard include built-in self-test (BIST), serial and parallel loopbacks, IDDQ (power down) and pseudo random bit sequence (PRBS).”
Also from Synopsys - The company announced that Toshiba Corp. has taped out a high-performance digital image processor chip using Synopsys DFT Compiler SoCBIST's deterministic logic BIST capability. The device has 6 million gates and was designed using Toshiba's TC280 0.13-micron process. Toshiba reported a 10x reduction in tester time and a greater than 100x reduction in test data volume using the tool.
Antun Domic, Senior Vice President and General Manager for the Synopsys Implementation Group, said: “Toshiba provided key guidance to Synopsys on their requirements in test quality, cost, and diagnostics, and has built a very impressive production methodology and design flow that fully and effectively utilizes SoCBIST's capabilities. We look forward to our continued collaboration with Toshiba and to advancing robust and production-ready manufacturing test methods for their next-generation products.”
Verisity Ltd. announced eAnalyzer, an “intuitive static analysis and verification methodology compliance system that simplifies verification environment development.” The company says the methodology is designed to allows engineers to adopt best practices at the module and system level by supporting Verisity's eReuse methodology (eRM) which is described as the foundation of the recently announced System Verification Methodology (sVM). The company says eAnalyzer facilitates verification component reuse, enabling easy creation of highly automated, high-quality, consistent chip-level verification environments using best-known guidelines. eAnalyzer will also support the IEEE P1647 version of the e verification language.
Also from Verisity - The company announced a new methodology, and “tightly coupled technology, that enables a 10x increase in productivity and improved predictability for automating the verification process at the SoC and system level. The System Verification Methodology (sVM) encapsulates comprehensive guidelines that effectively transfer specialized verification expertise, while new technology in the Specman Elite verification process automation solution and library additions simplify adoption and enable productivity gains required for the largest nanometer era designs.”
The company says that sVM provides productivity gains greater than 10x in the composition of SoC and system-level verification environments by raising the level of abstraction to the sequence level (combinations of transactions), while multi-channel constraint solving and generation makes it possible to get the same coverage goals in one-tenth the number of verification cycles as compared to directed testing or other customized methods.
The company says their announcements this week represent “another major step forward for Verisity's Verification Process Automation (VPA) strategy, going well beyond language and testbench toward automating and simplifying the increasingly complex process from executable test plans to verification closure. Verisity's VPA solutions combine pre-packaged, proven best practices with automation, analyses, and libraries in a form that can be readily adopted by the mainstream engineering community.”
ViASIC Inc. and Manhattan Routing Inc. (MRI) annouced a “strategic” partnership to enhance the timing closure flow and optimize low power design in large ASIC designs. Customers using MRI's optimization tool suite and ViASIC's routing technology will benefit by being better able to optimize the last few problem nets in a design. The companies say that the partnership will ensure that all design data exchange issues are resolved before customers use both companies' tools, and will give mutual customers “seamless” communication between the tools. ViASIC' s routing tool can use data from MRI's Physical Window and Optimization Cockpit tools either pre- or post-routing to optimize a customer's standard-cell design.
Coming soon to a theater near you
Ansoft Global Seminars 2003 - The company says these events will demonstrate how experts are threading electromagnetic analysis up front in their processes and rapidly creating optimized, high-performance designs. High-speed designers will hear about massively parallel supercomputer design, high-speed differential signaling, high-speed PCB signal launch, and so on. High-frequency designers will hear about optimizing high-performance LTCCs, amplifiers with Doherty configurations, cavity filter and diplexer deisgn, and so on. The seminars are happening in variuos venues throughout Asia, Europe, and North America. ( www.ansoft.com/DeliveringPerformance)
OEA International, Inc. announced that it has appointed two new distributors in India - ICON Design Automation Pvt. Ltd. - and Israel - AMOS Technologies, Ltd. - and added a dedicated sales representative in Europe. The company says the representatives will cover sales and coordinate product support. OEA recently opened a new sales office in the U.K.
SpiraTech Ltd. has announced that they have raised venture capital from two separate investment funds and appointed three individuals to the company's board. The company says the funding will be used to expand the company's existing customer base and develop its commercial potential on a global basis. The three new appointees include: David Stewart, CEO of CriticalBlue, who has joined the SpiraTech board in the capacity of non-executive Chairman, Chris Rose, Co-founder of Saros, who joins as a non-executive director, and Simon Calder, who has been named Vice President of Sales and Marketing for SpiraTech. Steve Hodgson, Co-founder and Managing Director for the company, is quoted in the Press Release: “Our industry now seems to be coming to the unanimous opinion that the migration from RTL to ESL has finally begun. In the past six months we have seen a dramatic increase in interest for our particular solution from SoC developers and other EDA companies alike. It is our aim to use this new capital to grow our team and to address the market needs for our products.”
Teseda Corp. announced the appointment of William Lattin to the company's Board of Directors and Roger Bitter to the role of Vice President of Sales. Lattin's resume includes: work at Motorola, Vice President and General Manager of Intel's System Group for 11 years, President and CEO of Logic Automation through its merger with LMSI to form Logic Modeling, President and CEO of Logic Modeling until the Synopsys acquisition, member of Synopsys' Board of Directors and Executive Vice President of Synopsys. Lattin has a PhD, holds seven patents, is a founding member of VHDL International, and a senior member of IEEE. He also serves on the Boards of six additional companies. Roger Bitter has 20+ years of sales experience in the EDA, IP, and ATE industries. Most recently he was Worldwide Vice President of Sales and Marketing at Xpedion. Previously, he worked at Virage Logic, Magma Design, Sycon Design, and was President and CEO of TSSI Inc. through to its acquisition by Credence. Bitter has a BSEE, an MS in Management Science, and an MBA in Finance from West Coast University.
Verisity, Ltd. announced that Pierre Lamond has retired from the company's Board and that Douglas Fairbairn has joined its board. Lamond, who has been on Verisity's Board since August 1997, will now focus on his private venture portfolio companies. Meanwhile, Fairbairn has over 30+ years of executive management experience in the semiconductor and EDA industries. Per the Press Release, he is a “recognized founder of the ASIC industry and system-level design segment of EDA. His previous positions include: Founder of VLSI Technology and General Manager of its ASIC Division, Founder and CEO of Redwood Design Automation, General Manager of the Alta Division at Cadence, President of the VSI Alliance SoC industry consortium, and President and CEO of Simutech Corp. Doug was also founder and Publisher of VLSI Design Magazine. Early in his career, he was a systems engineer at Xerox Palo Alto Research Center. He has BSEE and MSEE degrees from Stanford University.”
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