SystemVerilog in the news (again)

"Here at Cambridge, we have one of the most famous Computer Scientists in the world, Robin Milner, who basically invented process algebra together with Tony Hoare, who is now across the street at the Microsoft Lab. Many of the world's experts in programming language design have moved here and are now in one of our two research groups. Cambridge [is emerging] as the world's hotbed for advanced studies of new language concepts.”

“Currently, all of my new graduate students are working on high-level specification languages, the language constructs that are necessary for system specification. Creating a new language means different things to different people. [In a university setting], new languages are sketched out on white boards every day. However, it's a very different thing to translate those sketches into an industrial-strength standardized language.”

Industry News -- Tools and IP

Agilent Technologies Inc. announced that Thine Electronics Inc. has selected Agilent's high-frequency EDA tools to “help speed RF integrated circuit (RFIC) design.” Kazutaka Nogami, Director of Business Unit III at Thine Electronics, is quoted in the Press Release: “The ability to perform high-speed, frequency-domain simulation with Agilent's EDA tools has played an important role in the early release of our handset buffer amplifier RFIC, which was announced in July.”

Applied Wave Research, Inc. (AWR) and Sonnet Software, Inc. announced a circuit-to-EM integration. The companies say the integration will allow monolithic microwave integrated circuit (MMIC), radio-frequency (RF), and microwave engineers to translate circuit layouts between AWR's Microwave Office design suite and Sonnet's em software with the AWR EM Socket interface. Per the Press Release, “The EM Socket interface enables the Microwave Office software to directly interface with Sonnet for EM simulation. Users design in the Microwave Office environment and invoke Sonnet's EM solvers from a single user interface. Users familiar with Sonnet's XGEOM editor can also use this editor. Circuit layouts and simulation results are embedded directly into the Microwave Office object-oriented database.”

ASSET InterTech announced new features in their ScanWorks boundary-scan test and programming environment. The new productivity technology, which is called TopCAT (Topology and Cluster Analysis Technology), is included in the latest version of ScanWorks, Version 3.3.2. TopCAT analyzes the schematic of a PCB to identify all of the non-boundary scan devices that are connected to boundary scan devices. These non-boundary scan devices are candidates for boundary scan cluster tests. Next, TopCAT automatically matches the names of the non-boundary scan devices in the design's netlist with device models archived on ASSET's web site or stored in a model library within the user organization. Once the device models have been retrieved by ScanWorks' TopCAT technology, they are automatically included in the interconnect test generation process. Lastly, TopCAT optimizes the configuration of the device models in a test action for the highest test coverage and to ensure the safety of the board.

Atrenta Inc. and Aptix have announced a partnership to develop a set of RTL coding rules for pre-silicon prototyping that the companies say will ensure efficient mapping to Aptix's multi-FPGA prototyping platform. The rule-set is made available as the Aptix Policy for Atrenta's SpyGlass Predictive Analyzer, and is targeted for both design and verification engineers. The tool is intended to help both groups follow best practices and ensure code compliance with design-for-prototyping principles. For designers it provides a comprehensive set of rules around which to efficiently code their RTL for FPGAs. For verification engineers it ensures that they are receiving clean RTL while providing in-depth design information. Charlie Miller, Senior Vice President of Marketing & Business Development at Aptix, is quoted in the Press Release: “Aptix has more experience in pre-silicon prototyping than any other company. Part of our expertise is knowing the best way to design for prototyping. This new Aptix Policy for Atrenta's SpyGlass Predictive Analyzer captures that knowledge for use by our mutual customers.”

Barcelona Design Inc. announced that Sandbridge Technologies has licensed its analog synthesis solution for the fast creation of PLL circuits. Gary Nacer, Director of Engineering at Sandbridge, is quoted in the Press Release: “Because we serve the wireless handset market, power is of ultimate concern. Barcelona Design's synthesis solutions can generate full-custom PLLs, which satisfy our tight power budget while still meeting required high-performance specifications." Also per the Press Release, the PLLs will be generated using Barcelona's PLL synthesizer for the TSMC 0.13-micron “G” process. Sandbridge will use the circuits in its new SandBlaster DSP products for the wireless terminal market.

Giga Scale Integration Corp. (Giga Scale IC) introduced Time Architect, which the company describes as a “new class of electronic system level (ESL) virtual prototype software for fast, accurate estimation of chip size, power, cost and yield. Time Architect provides the umbrella over ESL design common in today's high-end ICs, and opens a new software category for the EDA industry. It allows electronic specification development for complex SoCs with full knowledge of the IC supply chain of libraries, memories, and IP. Specification can be evaluated for cost, size and power requirements. Finally, it obsoletes traditional IC-estimation methods that have evolved from pencil and paper to spreadsheet. Time Architect is based on Giga Scale IC's Technology Macro Modeling (TMM) for three to nine layers of metal, and process feature sizes ranging from 90 nanometers to 0.25 microns. TMM interprets standard data - LEF or Liberty, for example - describing semiconductor processes, libraries and IP to produce accurate macro models for area, power, clock and density evaluations.”

Magma Design Automation Inc. and Semiconductor Manufacturing International Corp. (SMIC), described as the largest foundry and ASIC design services provider in China, released a validated reference flow that incorporates the Magma IC implementation “solution.” The entities say that the flow was developed and validated using SMIC's 0.18-micron process technology using two SoC designs, and that support for other SMIC process technologies will be developed based on customer demand. Lung Chu, Vice President of Asia-Pacific Operations for Magma, is quoted in the Press Release: “We're pleased to partner with SMIC on this reference flow. I believe it will help our mutual customers achieve their area, timing, power, performance, manufacturability and reliability goals. This partnership, along with the technical support we are able to provide through our offices in Beijing, Shanghai, and Shenzhen, allows Magma to better support its customers in China."

Also from Magma - in a joint announcement with UMC, the company announced the availability of “the first fully validated, proven-in-silicon RTL-to-GDSII reference flow slated for chip designers utilizing UMC's 0.18-micron, 0.13-micron and 90-nanometer process technologies.” The flow can be downloaded from either company's website. The companies report that two mutual customers that have implemented designs using the RTL-to-GDSII flow include WIS Technologies and Faraday.

MIPS Technologies, Inc. announced that Fodus licensed the MIPS32 4Kc-processor core to develop SoCs for wireless routers, incorporating 802.11b/a/g wireless LAN access points, Ethernet switching routers, and firewall and VPN functions into one chip. Jeff Jen, President and CEO of Fodus, is quoted in the Press Release: “MIPS Technologies' highly scalable architecture gives our company the flexibility to upgrade future designs with minimal development effort.”

Synopsys, Inc. announced the availability of key components of Synopsys' Galaxy Design and Discovery Verification Platforms on Intel Itanium 2-based systems running the 64-bit Linux operating system. Rich Burnley, Director of CAD at Xilinx, is quoted in the Press Release: “In order to achieve the capacity we require to verify our latest programmable logic devices, we are running VCS 7.1 on 64-bit Linux systems based on the Itanium 2 processor.”

Synplicity Inc. announced it has made several “quality of results (QoR) improvements” to its Synplify and Synplify Pro FPGA synthesis software to provide “increased performance and area reduction for Xilinx devices.” The company says the latest versions of Synplify will “enable designers to increase the timing performance for their Virtex-II Pro devices by an average of nearly 10 percent compared with the previous version of the Synplify software. Additional enhancements to the software have been implemented especially for use in conjunction with Xilinx's recently announced Integrated Software Environment 6.1i (ISE). With these optimizations, designers can obtain significant area reduction in their devices often enabling them to use a smaller, less costly device, potentially saving tens or hundreds of thousands of dollars in device costs.”

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