High Priests & Gurus

The way we work across the team is fairly straightforward. Masaya will do models and then take those calculations to the group, providing prototypes in electrical form and explicitly listing equations. We have WebEx meetings with key EEsof development engineer Yo-Chien Yuan and other expert coders, and we discuss the implementation with them in detail. They tell us their requirements with regards to customer expectations and, of course, all along we're working with the EEsof project manager, Steve Chen, to meet a rigorous schedule. There are weekly technical meetings where we get down and dirty into the code.

It's actually been wonderful to see the synergy between our research and something commercial emerging from our work - something that's not only useful internally, but that has value when made public. As we're working with EEsof, we go out to visit customers and see a variety of problems. We see their facilities and their problems and we're able to deliver solutions.

Masaya: I echo everything that David has said. I don't have too much experience yet, but in this past year we've been meeting with customers and hearing about their issues and problems. It's been a great experience for me.

Joe: I've been with EEsof for 7 years, and the customer excitement I'm seeing with this Agilent HBT is really something. I'm not surprised that David and Masaya see that excitement as they're working with our customers.

David: It's been interesting to see the feedback from the customers. They've been very impressed that the physics is correct in the models and the ability of the models to accurately predict distortion. Importantly, these models are based on Masaya's work as a student - the link between distortion and the speed versus bias characteristics of the device. The customers are very appreciative of how well the models are behaving.

Masaya: I recently was able to visit customers in Japan to promote the model. They're exploring lots of uses for HBTs over there, including power amplifiers. Linearity is important in their applications, and I was encouraged by the positive feedback regarding the technical aspects of this model. They see value in the convergence aspects of our model as well - that the models simulate properly is a key issue with them.

David: The customers have been trying to use silicon-based bipolar models, but these are III-V HBT devices. The physical characteristics of Si BJTs and III-V HBTs are different. For instance, over much of the useful operating range, the speed of a III-V HBT decreases with increased collector voltage. In old-fashioned BJT devices, the speed increases with collector voltage. So it's the exact opposite. Most customers, if they try to fudge the parameters in those silicon models to fit an III-V HBT device, find difficulties and all kinds of hidden consequences. This leads to restricted and risky applications that are ultimately not the way to go about doing things. You need a real model of the actual device that you're using, a true III-V HBT model as opposed to a silicon BJT one.

In fairness, there's been good university work done in this area. The foundation of our work here in Santa Rosa was technical work done at UCSD. We've been working with Professor Asbeck at UCSD and Stretch Camnitz at HP, another key contributor, since their seminal paper was first published in 1996 incorporating the basic physics of these devices. There was a consortium between UCSD and HP back in the mid-90's - before we were Agilent - that also included Rockwell, TRW, Texas Instruments, Cadence, Silvaco, Meta-Software, the University of Illinois, and DARPA. That consortium was driving all of the work that resulted in the DARPA/UCSD model. The model implementation was a prototype with correct physics, but it wasn't a very commercially robust bit of code that could actually be used by a vast number of people doing design.

Since we had a close collaboration with Stretch, we started from the 1996 work and did some significant additional development to properly describe the operational physics of the non-linear transit time. We cleaned up some of the implementation details of the DARPA/UCSD model, extended it to InP devices - originally it was just for GaAs - and then EEsof robustly implemented it as commercial grade code. The consequences are that the model is more accurate, functions over a wider range of operating parameters, is more robust for convergence, and is faster than the DARPA/UCSD model. We definitely owe a debt of gratitude to Stretch and to Professor Asbeck, whose work went into the Agilent model.

Masaya: I have some brief comments. Peter Asbeck is a world-renowned expert on HBTs. I feel grateful that he was my advisor at UCSD. Basically, the majority of the work was done in the early to mid 1990s. Since then, there haven't been too many updates to the UCSD model. Presently, Asbeck is still doing research and mulling key issues, but the current efforts is not as a big as what led to the DARPA/UCSD model.

David: My Ph.D. was in abstract theoretical physics. It was abstruse work with no applications. When I came here to what was then HP, I thought I would be doing research on electromagnetism, but they changed their minds after I arrived. I was assigned to work on nonlinear models of transistors, even though I had never taken a single engineering course (except for one semester of linear systems - essentially applied mathematics) during my education. I didn't know what a transistor was! I only had a math degree and two physics degrees. It took a while for me to bring myself up to speed, but I think my background also freed me from the way in which other people had approached these problems in the past. I was lucky to be able to revisit the problems of nonlinear FETs and to examine the basic architecture of these HBT models.

It's been a long process for me, but I think my background in theoretical physics was beneficial. Now I feel I'm doing something useful. There's plenty of room for abstract physics and math in my work, but I'm also helping to solve problems that many people, young students, implementers, and engineers are working on and are interested in. The work is very diverse and interdisciplinary and exciting. I continue to learn each day from the many outstanding colleagues with whom I work. I have to say it's just been a wonderful experience here since the very beginning.

(Editor's note: According to Agilent: “Dr. David Root, Principal Scientist & Acting Tools Manager, Worldwide Process & Technology Centers, is an Agilent guru on high frequency modeling. He works in the company's Microwave Technology Center and has done research on device and behavioral models for years.” I ask you, what's the difference - “guru” versus “high priest.”

Meanwhile, it's actually quite frustrating at times to engage high priests in conversation. Whole hosts of questions come to you only later, days after the encounter has taken place. But by that time, they've gone back into their labs and the doors have been sealed shut once again. Nonetheless, my thanks to Caroline Melnicoff who worked her own special brand of magic to make this article happen.)

Industry News - Tools and IP

Accent announced that it has selected specification and estimation software from Giga Scale Integration Corp. (Giga Scale IC) to automate its current manual system for developing chip size, power, and performance estimates made in early stages of design. Accent says the company will standardize on Giga Scale IC's Time Architect, along with its IP database. Claudio Fasce, Vice President of Operations at Accent, is quoted: “Time Architect has tested well against our current proven methods and we found it provides very accurate estimates in a fraction of the time. We will rely on it to quickly provide chip size, IP reuse availability, architectural exploration and design migration estimates, helping us reduce the risk for all new designs.”

Apache Design Solutions has introduced two new versions of NSPICE. The company says that NSPICE-PI (Power Integrity) simulates extracted power-ground mesh circuits and other circuits containing an extremely large number of linear elements. Per the Press Release: “Simulations of netlists containing more than five million nodes, with more than 25 million RLC elements, multiple S-parameter blocks (each with 100+ ports all having their own reference), and more than 100,000 transistors can be done on a machine with 16GB of RAM at true SPICE accuracy.” Meanwhile, the company says that NSPICE-UBS (Ultrawide Broadband Simulation) simulates very high-speed circuits, and “offers the unprecedented capability to simulate multi-gigahertz signals requiring extremely small picosecond time-steps, over microseconds of time, such as high-speed serializer-deserializer (SERDES) circuits.”

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