Where the Rubber Meets the Road
All of this probably means the competition needs to sit up a little straighter, and take some serious notice of what's going on over at Novas.
PMC-Sierra, Inc. announced that PhatNoise, Inc. has selected PMC-Sierra's 400 MHz RM5231A 64-bit MIPS-based microprocessor for their next-generation car entertainment system. Dannie Lau, Co-founder and Executive Vice President at PhatNoise, is quoted in the Press Release: “PMC-Sierra provides a high performance, low power solution that meets the demands of the new features for our next-generation car entertainment system, and also allows us to seamlessly upgrade performance for future products while preserving code and dollar investments.”
Also from PMC-Sierra, Inc. - The company announced a licensing agreement with Integrated Technology Express (ITE) that allows PMC-Sierra to market and sell the ITE IT8172G System Controller under PMC-Sierra's branding. Jason Chiang, manager of product marketing, Microprocessor Products Division at PMC-Sierra, is quoted: “With this license agreement, PMC-Sierra will now be able to offer customers scaleable chip set solutions for multiple advanced consumer applications with the added convenience of one vendor. For networking and other applications, PMC-Sierra will continue to support other third-party partner solutions.”
Synplicity Inc. announced it has enhanced its Amplify FPGA physical synthesis and Synplify Pro FPGA synthesis software to include new support for Altera and Xilinx devices. The company says that with this new version, Synplify Pro offers new features to support the Stratix II family of FPGAs from Altera. Enhancements to Synplicity's Amplify FPGA physical synthesis software include support for a hierarchical timing report, faster timing closure, and support for the Spartan 3 family of FPGAs from Xilinx.
Per the Press Release: “With the latest versions of the Amplify 3.5 and Synplify Pro 7.5 software, Synplicity continues its efforts to deliver best-in-class performance for FPGA designers.”
Also from Synplicity - Looking forward, the company announced that it intends to offer timing estimation based on placement and automatic initial floorplanning as an alternative to traditional wireload model-based RTL synthesis in future releases of the Synplify ASIC software. The company intends to offer this technology free of charge to customers who are under maintenance at the time of release. The company says the new technology should help users reduce iterations between front-end and back-end design teams and provide more accurate estimates early in the design flow.
Also from Synplicity - The company announced the latest release of its Amplify ASIC software, which includes the company's new router-independent Sensitive Net Analysis and Prevention (SNAP) technology.
Per the Press Release: “The SNAP technology enables tight timing closure regardless of the back-end router used. First, specific routes in the design that are susceptible to significant timing variations due to possible routing choices are identified. Once identified, circuit topology around these sensitive nets is modified to remove router choices that lead to poor results. Synplicity has filed patents for this technology, which will be available in all future versions of Synplicity's ASIC physical synthesis tools - Amplify ASIC, Amplify RapidChip, and Amplify ISSP.”
Finally, and not surprisingly - Synplicity announced the “rapid adoption of its ASIC synthesis technology, including a doubling of ASIC synthesis license revenues in 2003 over the prior year.” The company says that since it entered the ASIC synthesis market in June 2001, 70 companies have purchased its Synplify ASIC and Amplify ASIC software, and 12 ASIC vendors have endorsed the software.
Synplicity says it attributes the success of its ASIC synthesis software to the tool's “industry-leading capacity and runtime, feature-rich functionality, plug-and-play compatibility with current ASIC flows and its focus on ASIC vendors and the design handoff market.”
Verisity Ltd. and ARM announced their collaboration to provide mutual customers with verification IP solutions to address the complexities of system-level verification. The two companies say they will jointly develop verification IP for the ARM11 core family, starting with the AXI e Verification Component (eVC), and advanced methodologies based on Verisity's VPA solutions.
Per the Press Release: “Many of the ARM semiconductor Partners are pushing the limit of system integration on a single chip. These designs, many of which are based on the ARM11 micro-architecture, require billions of verification cycles and hundreds of Gbytes of information, distributed over several compute and engineering resource locations. It is with this problem in mind that ARM has teamed up with Verisity to help ease the issues associated with the verification of these next-generation designs.”
Teseda Corp. and Agilent Technologies Inc. announced the first link that “ensures transportability of Design-for-Test (DFT) data between engineering and production test platforms. Customers of the Teseda V500 and the Agilent 93000 SOC Series can now quickly and reliably validate, debug, and apply IEEE 1450 (STIL)-based production test data generated by electronic design automation (EDA) tools. The net result is a test development flow that cuts weeks from time-to-money for many of today's semiconductor products.”
“Agilent and Teseda verified STIL transportability between the Agilent 93000 and the Teseda V500 using pattern files created by automatic test pattern generators (ATPGs) from leading DFT tool vendors, including Synopsys, Mentor Graphics, Cadence, and SynTest. The STIL files were imported into the two systems and validated as equivalent. Pattern edits were made on the V500 and the revised patterns were output in STIL by the V500 and then read into the Agilent 93000; these patterns were also validated as equivalent. This process ensures that DFT tests that run on one system will also run on the other with equivalent results.”
Virage Logic announced that MobilEye Vision Technologies used Virage's STAR Memory system to “reduce cost and increase reliability” in the MobilEye single camera driving assistance SoC chip, a product named EyeQ.
Per the Press Release: “The MobilEye EyeQ offers a solution for computationally intensive real-time visual recognition and scene interpretation. The chip architecture is designed to maximize cost performance by performing a full-fledged image application, such as a low-cost Adaptive Cruise Control, using a single video source on a single, ultra low-cost chip. The system can be used in a variety of automotive applications, including on side mirrors to alert the driver of cars coming from behind, inside the car to control the release of air bags based on passenger size, in adaptive cruise control, in forward collision warning, rain sensing, tunnel sensing, and much more. The STAR Memory System, which self-tests and repairs embedded memories, enables MobilEye and its customers to reduce manufacturing costs and deliver higher product reliability.”
Also from Virage Logic - The company announced that DongbuAnam Semiconductor and Virage have entered into a ”licensing and royalty-bearing agreement that provides for the delivery of Virage Logic's Technology-Optimized Platforms for DongbuAnam's new 0.13-micron CMOS processes. In addition, customers with designs featuring Virage Logic memory IP on the 0.18-micron process can now take their designs to DongbuAnam in order to take advantage of the price and performance benefits realized on DongbuAnam's 0.18-micron process technology.”
Coming soon to a theater near you
Semico Summit - The 7th annual Semico Summit Executive Conference will, per the organizers, “feature CEOs and industry executives sharing their vision of today's trends shaping the global semiconductor industry,” from March 14th to the 16th at the Marriott Camelback Inn Resort in Scottsdale, AZ. Panel topics are set to include: Where Is Our Industry Now; The Next Killer App; and Strategies for Moving Forward in Bringing Products to Market in the Deep-Submicron Era. All of these subjects, and more, should be of interest to those inclined to attend. http://www.semico.com/summit04/registration.htm
Mentor Graphics User Group Conference - The company's 20th annual meeting, User2User, will be taking place April 19th to the 21st at the Santa Clara Marriott in Santa Clara, CA. The conference program includes 100+ technical presentations selected from 140+ user-submitted abstracts submitted, as well as presentations by Mentor Graphics personnel. Organizers say the keynote address will be delivered by the in-your-face (my judgment, not Mentor's) computer columnist and media personality John Dvorak. A contributing editor of PC Magazine, Dvorak's work appears in several magazines and newspapers. He's also authored several books. (www.mentor.com)
Synopsys Technical Seminar Series - The company announced its annual technical seminar series - addressing mixed-signal, functional verification, and implementation solutions - will begin in February and will take place in a variety of worldwide venues. The seminar is described as a “forum for members of the electronic design community to get the most recent information on design automation products, methodologies and processes. Intended for designers, developers, verification engineers and managers, these free in-depth technical sessions discuss the latest technological advances and future trends of Synopsys' leading EDA tools and solutions for mixed-signal design, functional verification and implementation.” ( www.synopsys.com )
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