1st International System-on-Chip Conference
In December 2002, the IPFlex and Fujitsu formed an equity collaboration. In March 2004 the two firms announced the commercial release of their jointly developed processor, the DAP/DNA-2 (Digital Application Processor/Distributed Network Architecture). They expect to begin shipping sample quantities in Japan in mid-May.
DAP/DNA dynamically reconfigurable processor is designed as a dual-core processor comprised of a high-performance RISC core (DAP) and a dynamic reconfigurable processor core (DNA), and it is a platform that provides hardware performance while maintaining software flexibility. The DAP/DNA dynamic reconfigurable processor series is provided with the DAP/DNA-FW II as the integrated software development environment. It provides compilers for algorithms written in MATLAB/Simulink and C with data flow extension, thus realizing high-abstraction level algorithm design as well as leveraging existing intellectual properties of users.
The DAP/DNA-2 is a microprocessor that contains multiple processing elements (PEs) and can optimally configure internal circuits to best suit the application in demand. The function of each PE, as well as connections among PEs, can be reconfigured not only when building the system, but also when it is running, enabling instant (within one clock cycle) reconfiguration to suit the application at hand. The DAP/DNA-2 lays out these PEs in a two-dimensional array so that it can quickly and flexibly change their function and the connections between them.
Using dynamic reconfiguration technology makes it possible to process multiple functions with a single DAP/DNA-2 that previously required several specialized chips. Also a single algorithm could be partitioned in time for execution. DAP/DNA's integrated development environment enables algorithm development in high-level languages. This capability increases design productivity, shortens the development time and slashes cost.
During one of the panel discussion the question arose concerning the degree to which programmability and configurability could “future proof” a product. It was readily conceded that one could exploit these capabilities to support multiple members of a product family, fix bugs, add features, and adjust to changing protocols. However, the approach has its limits. The consensus was that the Product Marketing function could not be eliminated. Someone has the responsibility to look ahead in time and across product lines to foresee future feature set, performance, power and cost requirements. There is a tradeoff of overhead today for headroom tomorrow.
Weekly Industry News Highlights
Novas Expands Deployment Of Debug System Within Ricoh's Electronic Devices Company
Solution for Wire Harness Design Cuts Cabling Weight, Size and Cost While Optimizing Performance
Mentor Graphics and X-FAB Provide New Production-Proven Design Kits for Mentor's Mixed-Signal IC Design Flow
Magma Signs Multi-Year Worldwide Licensing Agreement with NEC Electronics
Esterel Technologies and ENSCO Inc. Team on Products and Services for Safety-Critical and Mission-Critical Applications
Toshiba Tapes Out Multiple 90-Nanometer SoC Designs With Synopsys' Galaxy Design Platform
Magma Announces Support for Virage Logic Structured ASIC Design Libraries
Freescale Semiconductor Reveals PowerPC(R) Core Roadmap and Scalable System-on-Chip Platforms
Atmel Introduces a PC7447A Microprocessor for Extended-Reliability Applications
VCX Software To Provide IP Data, Supply Chain Capabilities to Chip Estimation and Optimization Expert Giga Scale IC
Giga Scale IC Rouses Electronics Industry with InCyte; Industry's First Specification, Optimization Tools Model Nanometer Physical Effects
More EDA in the News and More IP & SoC News
--Contributing Editors can be reached by clicking here.
Be the first to review this article