Low Power Soc Design


Sub-threshold leakage current is proportional to exp[q(Vgs-Vt)/nkT]. According to this relationship, leakage current and therefore power dissipation increases exponentially with decreasing threshold voltage and with increasing temperature. Of course using high-Vt transistors will degrade performance. A solution is to have a mixture of high and low Vt transistors. Use low Vt transistors on timing-critical paths and high Vt transistors on non-critical paths. This approach is referred to as dual Vt design.

Multi-Threshold CMOS (MTCMOS) cells can be used to control leakage power. Low Vt transistors are used to implement gates for high speed, while high Vt transistors are added to form virtual rails. These high Vt transistors suppress the leakage current when the Sleep signal is activated. Of course there needs to be a sleep control mechanism



Variable Threshold CMOS (VTCMOS) is a body biasing technique that controls effective threshold voltage by applying substrate bias to MOS transistors. In the active mode a zero body bias is applied. In standby mode, the effective threshold voltage is made to be larger by applying a reverse substrate bias to block the leakage current. Transistor performance in the active mode is kept the same as that in the conventional design by utilizing low VDD and low Vt.




Other issues

Thus far we have focused on the need for and the methods of reducing power consumption and dissipation. There other factors such as temperature, timing, signal integrity and reliability which are impacted by power design decisions and need to addressed.

IR drop is a supply voltage reduction across a large IC as current flows through its power grid. The voltage drop may causes the voltage supplied to the affected cells to be lower than required, leading to larger gate and signal delays, which in turn can cause timing degradation in the signal paths as well as clock skew. Voltage drop on power and ground grids also reduces the noise margins and compromises the signal integrity of the design. The IR-drop effect in the power/ground network increases rapidly with technology scaling. Traditional counter measures include wire-sizing and decoupling capacitor insertion with resource allocation schemes.

The effects of changes in supply and bias voltages on timing and power must be characterized. In the past k-factor based derating functions in .lib format sufficed. Today, more advanced equation-based methods using Scalable Polynomial Models (SPM) are required.

Electromigration (EM) is the flow of metal ions under the influence of high electric current densities resulting in the depletion and accumulation of metal ions along the interconnect. The migration of material caused by electron “wind” creates voids upwind and causes metal ions to accumulate downstream into “hillocks” or “whiskers,” In power grid wires, the increased resistance due to EM can result in larger IR drops and degradation in gate delay. Power EM is harmful from the point of view of design reliability as the voids can cause open circuits, while the hillocks tend to cause shorts in neighboring wires. EM is dependent upon temperature, current densities and the length and width of wires. In the case of signal lines the two main forms of EM are referred to as the wire self-heat and hot electron effects. Wire self-heat occurs when the current density is too high. The resulting heating effect causes the affected tracks to expand and contract, which degrades the reliability of the design. The hot electron problem refers to the case where carriers become trapped in a transistor's channel. This distorts the field used to control the transistor, which results in performance degradation.



Vendors

How are some representative vendors responding to the challenges of low power design in terms of estimation, synthesis, optimization, and analysis offerings? Thumbnail sketches follow.

Atrenta a venture funded ($17 million) spin-off of Interra, Inc started in 2001. The company's core product, SpyGlass, is a predictive analyzer that can do in-depth structural analysis at the RT-Level through the use of its unique “look-ahead” architecture that is based on fast-synthesis and cycle-based simulation engines. SpyGlass is able to quickly identify critical problems such as combinational loops, synchronization across multiple clock domains, tri-state bus decoding errors, and wasted real-estate.

Atrenta offers a number of application specific tools including SpyGlass LP - designing RTL for low power. LP analyzes designs for low power issues at the block level and chip level. It helps visualize voltage (power) domains, examines issues related to signals crossing domain boundaries and assists with clock gating. It also employs a switching analysis engine and a comprehensive rule set.

SpyGlass LP is part of a comprehensive analysis solution that includes checks for complex design problems such as clock domain crossings, synchronization, set-reset, area, electrical rule checking, design-for-test, and constraints validation.

Sequence Design, Inc. was formed in June 2000 by the merger of Frequency Technology and Sente, Inc. In January of 2001, Sequence merged with Sapphire Design Automation. Today the company has 90 employees. I spoke with Piyush Sancheti, Director of Marketing. Sequence offers four distinct families of software solutions: PowerTheater for efficient power design, CoolTime for electrical integrity analysis, PhysicalStudio for design closure and ExtractionStage as an extraction tool.

PowerTheater is focused at the architectural level where 80% of the power consumption is determined. The methodology is to estimate power early, optimize power dissipation before synthesis and to verify power at the gate and physical level. Sequence has developed a sophisticated RTL divide-and-conquer approach, where both static and dynamic power is accounted for. PowerTheater identifies the major structures in the design and then focuses specific, patented power analysis methodologies on these structures, including: memory, I/O's, clocks, data path and control logic to identify power-reduction opportunities. It proposes RTL design modifications along with estimated power savings.

CoolTime offers electrical integrity analysis for the concurrent analysis of power, voltage drop, timing, and signal integrity. It uses event-driven timing windows and dynamic coupling models to accurately model crosstalk delay and glitch. CoolTime's instantaneous analysis is based on a patent-pending vectorless algorithm, T2, for current and voltage calculation. This unique algorithm relies on static timing analysis methods to compute actual event waveforms on each circuit node. Based on the switching events and power data in the .LIB, CoolTime computes instantaneous current waveforms and resulting voltage waveforms. The voltage analysis takes into account the dynamic effects resulting from power grid capacitance, on-chip decoupling capacitors and package inductance. Additionally, simulation based instantaneous and average methods are also supported utilizing switching activity in VCD format.

Last May Sequence Design announced a joint development effort with Toshiba Corporation to optimize power and reduce wasted power consumption in semiconductors based on Toshiba's Selective MTCMOS (Multi-Threshold CMOS) technology. Last week Sequence Design announced it has entered into a partnership with the power driven physical design EDA vendor, Golden Gate Technology, to add power grid design to the company's NanoCool power integrity flow.

I recently attended a one day seminar on Low Power Soc Design hosted by Magma Design Automation the number four EDA vendor according to our quarterly reports. After the seminar I also spoke with Sameer Patel, Director of Product Marketing. He stressed the differentiation was their unified memory resident data model that enables the optimization, implementation and analysis engines to get immediate access to continuously updated logical, physical, timing and other design information for making on-the-fly design decisions. He said that these was far more integrated then merely having a common data repository that required individual modules to extract information, massage it and redeposit it.

Magma offers two power modules Blast Power and Blast Rail that are fully integrated into its RTL-to-GDSII implementation flow.

Blast Power is Magma's solution for power optimization and management. Power-aware synthesis supports techniques such as clock gating, power gating, voltage islands, and multi-Vt libraries. An optimization engine makes leakage-power-versus-timing tradeoffs through the design and implementation flow. Power-aware placement and routing minimizes switching power and ensures uniform power and voltage drop distribution.

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