Silicon Laser and Cell Processor

Raman Effect

When light is scattered by a molecular system, most of the scattering is elastic or Raleigh scattering where the emitted photon has the same wavelength as the absorbing photon from the incident light. However, a small fraction of the scattering is inelastic, an effect discovered by Indian physicist C. V. Raman in 1928. In Raman scattering, the energies of the incident and scattered photons are different. The energy and thus the frequency and wavelength of the scattered light is changed as the light either imparts energy to the scattering molecules or takes energy away. If one measures the scattered light as function of wavelength most will be found to have the original wavelength of the incident radiation and a much smaller portions will be found corresponding to the shorter or longer wavelengths of the altered portion of the light. This Raman spectrum is characteristic of the transmitting substance and thus can be used as a basis for spectroscopy. If the initial beam is sufficiently intense and monochromatic, a threshold can be reached beyond which light at the Raman frequencies is amplified, builds up strongly, and generally exhibits the characteristics of stimulated emission.

The Raman effect is widely used today to make amplifiers and lasers in glass fiber. However, fiber-based devices using the Raman effect are limited because they require kilometers of fiber to provide sufficient amplification. The Raman effect is more than 10,000 times stronger in silicon than in glass optical fiber, making silicon an advantageous material. Instead of kilometers of fiber, only centimeters of silicon are required.

The fabrication of a silicon laser begins with the creation of a waveguide by etching a ridge or channel into a silicon wafer. Light pumped into this waveguide will be contained and channeled across the chip. In any waveguide there is a loss of light due to a variety of factors. Intel researchers discovered that that increasing the pump power beyond a certain point no longer increased the amplification and eventually even decreased it. This reduction was due to so-called two-photon absorption process. It is possible for two photons to arrive at an atom at the same time in such a way that the combined energy is enough to free an electron from an atom. These free electrons build up over time and absorb some of the light passing through the silicon waveguide thereby canceling out the Raman amplification.

Intel's solution was to change the design of the waveguide by embedding it within a semiconductor device, a reverse-biased p-i-n (P-type - Intrinsic - N-type) junction diode. It is formed by implanting a short region on each side of the waveguide with impurities that convert silicon into a material with electron (n-side) or hole (p-side) conduction. When a voltage is applied to this device, it acts like a vacuum and removes the electrons from the path of the light.

The silicon laser could lead to many applications including optical amplifiers, wavelength converters, and various types of lasers in silicon. Optical communications and silicon photonic technology will allow enterprises to scale bandwidth availability to meet the needs of network infrastructure.

Cell Processor

In November 2004 IBM, Sony, Sony Computer Entertainment and Toshiba first unveiled some of the key concepts of their Cell processor, the result of a four-year collaborative effort. At that time Boris Petrov, managing partner of the research firm Petrov Group, commented that "The year 2004 marks the birth of a distinctly new cellular computing era. As with past watershed computing events, the driving and trend-setting force will be IBM. While I shy away from hyperbole, our report demonstrates that the business impact of IBM's new cellular computing technology will be potentially as profound as the Yucatan asteroid's was on life on Earth millions of years ago." What marketing manager would not give his soul for a quote like that? Masayuki Chatani, corporate executive and CTO, Sony computer Entertainment Inc, was a tad more restrained when he said that "The Cell processor-based workstation will totally change the digital content creation environment. Its overwhelming power will be demonstrated in every aspect of the development of all kinds of digital entertainment content, from movies, broadcast programs to next generation PlayStation games."

This level of hype is obviously quite a lot to live up to. Sony intends to use the Cell chip in its Sony's PlayStation 3 video console as well as in home servers and high definition television (HDTV) in 2006, Toshiba plans to use the Cell in digital television sets and IBM intends to put it in computer servers and work stations. The fact that all three firms involved will incorporate the Cell chip in mass market products (Sony PlayStation2 sold 89 million units by the end of 2004) will help ensure its success.

The press releases did not go into very much detail. Some technical analysts have poured over the patent application in order to ferret out some of the technical nuggets.

The Cell chip will have 234 million transistors, measures 221mm2 and be produced using advanced 90nm silicon-on-insulator (SOI) processes.

Among the highlights of Cell processor:
- Cell is a breakthrough architectural design -- featuring eight synergistic processors and top clock speeds of greater than 4 GHz (according to hardware tests)

- Cell is a multicore chip capable of massive floating point processing at 256 gigaflops

- Cell is OS neutral and supports multiple operating systems simultaneously including real-time consumer electronics and game console operating systems.

- Resource management system for real-time applications

- On-chip hardware in support of security system for intellectual property protection

- 6.4 Gigabit / second off-chip communication

- 2.5 MB on-chip memory (512KB L2 and 8*256KB)

- Autonomic power management
The Cell is an asymmetric design with two types of processors. A 64-bit RISC PowerPC processor acts as a PPE (Primary Processing Element). The main cell processor supports dual-threaded (SMT) operation, using a 32KB L1 cache and a 512KB level 2 cache. There are also eight sub or helper 32-bit units acting as SPEs (Synergistic Processing Elements). Each of these "cells" has 256KB of private Load Store (LS) memory, a 4 x 128 bit ALU's (Arithmetic Logical Unit), and 128 x 128 bit registers. These vector processors serve as standalone Alternate or Attached Processing Units (APUs) executing APUlets. The APUs operate on registers which are read from or written to the local memory. This local memory can access main memory in blocks of 1024 bits.

The SPE's can be chained together in a steaming mode. The system accepts data and processes it in a series of steps that can be performed by one or more SPEs. Data is read into the local memory of one unit, processed and written to RAM accessible by other SPE units.

The SPEs are connected to each other and to a 512KB L2 cache via an Element Interface Bus (EIB) that consists of four 128-bit wide data channels. The individual SPEs can use this bus to communicate with each other, and this includes the transfer of data in between SPEs acting as peers on the network. The SPEs also communicate with the L2 cache, with main memory via the memory interface controller (MIC)

According to Rambus, Inc the Cell processor incorporates Rambus's XDR memory and FlexIO processor bus interface solutions. The memory and processor bus interfaces designed by Rambus account for 90% of the Cell processor signal pins, providing an aggregate processor I/O bandwidth of approximately 100 gigabytes-per-second. The Rambus XDR (eXtreme Data Rate) memory interface is capable of data rates of 3.2GHz to 8.0GHz. FlexIO processor buses, formerly codenamed Redwood, are capable of running up to 6.4GHz data rates. FlexIO interfaces provide a low-latency and low-power solution for high-volume, low-cost applications, including processor, chipset and network chip connections for a broad range of applications. FlexIO employs DRSL (Differential Rambus Signaling Level) with LVDS (Low Voltage Differential Signaling). Sony and Toshiba signed a licensing agreement with Rambus in January 2003.

The architecture is optimized for compute-intensive workloads and broadband rich media applications, including computer entertainment, movies and other forms of digital content.

The processing power of 256 gigaflops is truly impressive but would not land this "supercomputer on a chip" on the current list of the Top 500 Supercomputers.


Review Article Be the first to review this article
Featured Video
Currently No Featured Jobs
Upcoming Events
MAPPS 2018 Summer Conference at The Belmond Charleston Place Charleston SC - Jul 22 - 25, 2018
International Test Conference India 2018 at Bangalore India - Jul 22 - 24, 2018
SRTC-2018 at The Leela Ambience Gurugram NEW DELHI India - Jul 25 - 26, 2018
MPSoC Forum 2018 at The Cliff Lodge 9320 South Cliff Lodge Drive Snowbird UT - Jul 29 - 3, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise