Mentor's Questa Verification Products

According to the latest EDAC numbers Mentor is now the largest verification company having surpassed our friends at Cadence. Analog, mixed signal, functional verification, emulation and so on. People choose their simulators based upon the productivity they get in verification. The statistics you get from Ron Collett is that verification takes up 60% to 80% of the overall design cycle. Simulation is used very early when people start writing RTL. They start to package it up and test. There are enough standards in place, Verilog and VHDL where you can capture in one vendor's tools and verify in another. The point of standardization is that they can have flow even if they do not buy all of the tools from one vendor. We still manage to differentiate the kind of value we offer.

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TransEDA announces Assertain™, the first independent Verification Closure Management tool. Covering all front-end design stages from original text specification through to validated RTL, Assertain monitors, measures and manages the verification process in one integrated environment. The tool seamlessly brings together rule, protocol and assertion checking; code and assertion coverage; design and assertion coverability analysis; test grading and optimization, linked to specification coverage using proven requirements traceability techniques.

Mentor Graphics Users Conference (U2U 2005) Proceedings Papers Now Available

Mentor Graphics Strengthens its Automotive Solutions Portfolio with the Acquisition of Volcano Communications Technologies. Volcano's automotive networking series includes network design tools, embedded software and test and validation tools for all major automotive networks. Terms of the deal were not disclosed.

New Cadence PowerMeter Technology Enables Signoff-Quality Dynamic Power Rail Verification; VoltageStorm Dynamic IR Drop Analysis Enhanced with Sophisticated Power Consumption Analysis Capabilities. PowerMeter enables design teams to accurately calculate and distribute leakage, internal and switching power consumption for every instance of their design

Celoxica ESL Tool Gets Faster and More Physical; The Leading ESL Design Suite for Algorithm Acceleration Sets New Standards in Performance and Ease-of-Use, Optimizes the Connection to SoC Flows. DK4 introduces new VHDL and Verilog output optimizations for interfacing with Design Compiler from Synopsys. In addition to RTL input for the SoC flow, DK4 also supports automatic scripting for SoC test bench generation. This interface bridges the gap between ESL and latest SoC physical design and verification flows.

Other EDA News

Calypto and Mentor Graphics Integrate Tools for Verifiable, Automated Path from System to RTL; Calypto Joins Mentor OpenDoor Program

EVE, Novas Complete Integration Between EVE's Hardware-Assisted Verification Platform, Novas Debug System; Optimized Tool Flow Streamlines SoC Debug with EVE's ZeBu

OEA International Enhances DP-PLAN™, Dynamic Power Planning Tool with Visual Feedback

OEA International Boosts Performance of P-GRID™ Power Distribution Analysis Tool

OEA International Boosts NET-AN™ 3D Critical Net Extractor Performance for Nano-Meter Technologies

Design For Debug Meeting To Be Held At 42nd Design Automation Conference

Cadence President & Chief Executive Officer, Mike Fister, to Present at the SG Cowen Technology Conference

At DAC 2005 OEA International Invites You to Attend High Speed Digital & RF Design Presentations and Demos

OEA International Announces Enhancements to Spiral Inductor Design and Synthesis Tool

Summit Design Expands Its ESL Solution Suite with Vista 1.1 to Deliver Advanced Analysis and Debug for Expert and Novice SystemC Users; Powerful Automatic Transaction-Level Modeling Viewer Provides Comprehensive System-Level Design Observability

HP Strengthens Adaptive Enterprise Solutions with New Offerings; Company Launches World's Most Reliable Server, First Unified Infrastructure Management Software

Silicon Dimensions adds new levels of POWER analysis, modeling and prediction to Chip2nite

VaST Systems Releases Virtual Processor Model Transformer, Latest in Line of Powerful "Constructor" Tools

Sigrity Solution Optimizes IR Drop Analysis for Packages and Boards

Huawei Adopts Synopsys VCS Native Testbench to Accelerate Verification of Networking and Communications ASICs

Synopsys Advances VCS Solution by Adding Assertion IP Library and Native Testbench Support for SystemVerilog

Other IP & SoC News

EZchip Doubles the Price-Performance of 2.5-Gigabit Network Processors; Provides the NP-2/5, a 5Gbps duplex NPU with 10xGE ports and Traffic Manager

TI Provides Free SPICE Circuit Simulation Program for High-Performance Analog Designs

SiRF Technology Acquires Motorola's GPS Chip Set Product Lines

Agere Systems Announces Money-Saving Software, a Higher-Performance Network Processor, and Multiservice Convergence Demo at SUPERCOMM

Cygnus Communications, Inc. Completes Acquisition of SiWorks, Inc.

Conexant Unveils Complete Family of VDSL and VDSL2 Semiconductor System Solutions; Accelity Production Chipsets Shipping to Customers for Global VDSL2 Deployments

AMCC Demonstrates ATCA-Based, Multiservice Evaluation Platform at Supercomm 2005; Enables OEMs to Drastically Reduce Costs, Risk and Time-to-Market When Developing Next-Generation Networking Solutions

TI Introduces Class-D Audio Power Amplifier for Flat Panel Displays

Fairchild Semiconductor Updates Guidance for the Second Quarter

FSA Finds Funding of Fabless Companies Rises 36% QoQ; Segment Raised $357.9M in Q1 2005

Actel Broadens Popular PCI Product Family With CorePCIF

National Semiconductor Introduces Energy-Efficient, Integrated AC-DC PWM Controller For Power Systems

TDK Corporation announces Acquisition

TI and RadioScape Launch First Chips and Modules for Digital Radio Mondiale Standard

Altera Narrows Second Quarter Revenue Guidance

New Analog Devices Instrumentation Amplifier Delivers Precision Performance to Low-Voltage Applications

Zarlink Introduces World's First Wireless Chip Designed Specifically for In-Body Communication Systems

Atmel Announces First High-Speed 8-bit MCU With Integrated USB to Serial Bridge Interface Capabilities

Atmel Introduces AVR Microcontroller-Based 13.56 MHz Contactless Smart Card Reader

Virage Logic Joins With TSMC to Lead 65nm Ramp

Global Semiconductor Sales Show Slight Decline in April; Chip Sales up by 7 Percent from April 2004

FLCOS technology could achieve $999 microdisplay TV, say CRLO execs - EETimes Article

Artimi enters UWB fray with single-chip option - EETimes Article

More EDA in the News and More IP & SoC News

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