Structured ASICs ala eASIC


How many employees at eASIC?
We have about 90 employees.

Are these employees centrally located or spread around?
We have about 70 of them in Romania. The development has been carried out primarily in Romania with VP and lead managers located here.

Why Romania? Did the founder have some connections there?
There was a connection with a prior company. Our founder was also founder and CEO of ChipExpress. There was a Romanian connection there. He was able to continue some of those connections when he founded this new company. In addition to the 70 Romanians we've just opened a development office in Penang, Malaysia. We're in the process of hiring and recruiting for that office.

I'm assuming that the rationale for going to Romania and now Malaysia has to do with the cost of talent.
I'm sure you've reported on this aspect of our industry at length. What I would say is that it is a combination of factors. One is cost and the other is the experience that one can get and the ability to retain that. Retention has its good side and its down side. The good side is that you can keep employees productive as well as part of a team, a team that works well together. The downside is that you don't tend to get a lot of new experience into the company. So it's a combination of these factors as to why we have chosen these countries. In Romania you have a combination of raw math and engineering talent that we can retain. When you train them its easier to retain that team and keep them together as a working team. The downside is that you don't tend to get a lot of experience into the company; people with ten years. In Malaysia you tend to get people of that caliber as well. So a combination of factors - retention and the ability to hire experience people.

At a high level there are three markets out there, namely standard cell ASICs, structured ASICs and FPGAs. Could you characterize those three?
In general standard cell is a $20B market. The numbers vary slightly but the number of design starts vary between 1,500 and 2,500. It's relatively high revenue per design. Some of the very high revenue products like cell phones can swamp them but the general nature of that business is the cost of development and of development time has increased. The general nature is that you end up with high revenue per design requirement to start the design. The benefit of the design is that you can optimize that design for its end application and for its performance. That's the most optimized way of doing custom logic design which people outside of microprocessor do these days. At the other end of the spectrum is FPGAs. The number of design starts depending on whom you believe is closer to 80,000 or 100,000. The total revenue of that market is about $3B. You can see that this market is exemplified by very little revenue per design start. Some of those design starts don't actually result in any revenue. The reason for that is that it is the least optimum for the end application. You're starting off with a generic chip and you're trying to fit your design into that generic chip. So just by its nature it's a less optimized approach. They tend to consume large amounts of power, probably 400x the power of a standard cell. They tend to be much lower in performance, probably at least one fourth the performance of a standard cell. They tend to be a lot larger. The largest chips tend to be 2cm. They tend to be very costly. The benefit of them is that they are off the shelf components that you can match with the design environment and you can pretty much implement your design relatively quickly. It's getting more complicated as technology moves forward. Once you've done that design, if something is wrong you can remap your architecture or functionality again and again. So they are a verification vehicle and that's what they tend to get used for; prototyping and verification vehicles. Whereas a standard cell tends to get used as a production vehicle.

What has happened over the course of the last two or three years is that the gap between the two has widened. Some people would say that the gap has closed but it has actually widened because the capability of the standard cell has increased so much. But the cost of designing in advanced technology has also increased.

Along comes structured ASICs or platform ASICs, that's the product that you make some tradeoffs with. You may not get the most optimum implementation - die size, power and performance - but you can meet your needs. You don't get the absolute ability to reverify your functionality that you would get with an FPGA but what you do get is a faster turnaround time in design and manufacture. So you are making some tradeoffs. Most people are able to live with those tradeoffs, meaning design time becomes shortened and more predictable, the die size isn't much larger and in fact you can ship up to certain numbers of units in volume and feel very comfortable in doing so from a market penetration perspective. What happens now is that people are able to start over again designing in hardware customization. Before they had started to stop doing that. That's where structured ASICS fit in.

Why did I join eASIC? I believe that they have a unique and compelling proposition within that structured ASIC approach and also embedded IP within the standard cell approach. You really hopefully start to reverse the trend of standard cell design starts declining and actually increase them by embedding our technology in there and allowing all the customization of the chip. We are basically building customizable platforms as opposed to real ASICs.

If structure ASICs is a compromise between two extremes, is there a risk that no one would be satisfied? Is there a major market for this?
There is definite a major market for this. You're not wrong when you said that. The challenge is making sure that the tradeoffs one is making and the approach you're taking to this market are beneficial to the customer. There's definitely a large market for this type of product but you don't want to create a product for this market that is say half the cost of an FPGA. You want to create a cost differential that's markedly compared to the unit price of an FPGA. At the same time you've got to make the design faster and significantly less costly than the standard cell design. You've got a few parameters, a few knobs to twiddle and turn till you get the right wining solution. I think the experience in this market has shown, I've worked a lot in the standard cell world and spent a significant time looking at he FPGA world. I think we know where those knobs, those dials that need to be set for it to be meaningful Underpinning that as an example eASIC has a one via stage customizable approach which essentially means no masks are need to be made, there's no upfront NRE. STMirco was able to show with our technology that they were able to get RTL to GDS II in 24 hours. We are cutting the cost of design as well as significantly cutting the NRE costs. The chip price is not significantly different in volume from that you would get from a standard cell because our density ranges from half a standard cell to actually 2X density in one benchmarking. Turning these knobs exactly right is very important.

How do you deliver your product? Do you have wafers stored somewhere?
The final product is delivered as chips to the customer. We're a fables company so we deliver chips at the end of the day. The product enables them to get to that point is the design environment that we provide. We have a partner we are working with, Magma, who provides tools that support our design environment. Then we provide the libraries. We work with third party IP providers as offer our own IP to the customer.

« Previous Page 1 | 2 | 3 | 4 | 5  Next Page »

Rating:


Review Article Be the first to review this article

EMA:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Retail Therapy: Jump starting Black Friday
Peggy AycinenaIP Showcase
by Peggy Aycinena
REUSE 2016: Addressing the Four Freedoms
More Editorial  
Jobs
ACCOUNT MANAGER MUNICH GERMANY EU for EDA Careers at MUNICH, Germany
Principal Circuit Design Engineer for Rambus at Sunnyvale, CA
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
AE-APPS SUPPORT/TMM for EDA Careers at San Jose-SOCAL-AZ, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Upcoming Events
Zuken Innovation World 2017, April 24 - 26, 2017, Hilton Head Marriott Resort & Spa in Hilton Head Island, SC at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy