Synopsys DesignWare(R) PHY IP Enables Reliable USB Connectivity for IBM and Chartered Foundry Customers
IBM and Chartered collaborated with Synopsys to ensure that the DesignWare USB IP solution, which includes mixed-signal PHYs, digital controller cores and verification IP, is optimized for the companies' 90-nm common process platform. Proven in 180-, 130- and 90-nm, the DesignWare USB 2.0 and OTG PHYs passed through rigorous electrical and interoperability tests by the USB Implementers Forum and have been used by designers in a number of market-leading high-volume products. DesignWare USB PHY IP design kits include simulation models, documentation and GDSII layout information, which minimizes integration and verification time designers spend adding USB connectivity to their system-on-chip (SoC) designs.
"Making Synopsys' USB 2.0 IP available to designers using the IBM-Chartered common process platform is an important part of our open platform strategy," said Walt Lange, field executive, Systems Solutions at IBM. "Their ability to provide a competitive solution including verification IP within the design flow is a key enabler for our customers using USB 2.0 interfaces."
"Synopsys is one of the leading providers of PHY IP and we are pleased to be working with Synopsys on the 90-nm common process platform," said Kevin Meyer, vice president of Worldwide Marketing at Chartered. "The competitive die size and power consumption of the Synopsys DesignWare PHYs, combined with the complete USB digital controller IP offering, enable designers to quickly add cost-effective USB connectivity in applications like high performance game machines, office peripherals, and battery powered portable audio and video devices."
"IBM and Chartered are enabling customers to realize the benefits of their 90-nm common process platform with Hi-Speed USB connectivity," said Guri Stark, vice president of Marketing in Synopsys' Solutions Group. "Our collaboration with these leading companies to provide key IP design components will enable SoC designers to quickly achieve cost-effective volume production."
The USB 2.0 design kits for the Chartered and IBM 90-nm common process platform are expected to be available in Q3 of 2005. DesignWare controllers and PHY IP for Hi-Speed USB OTG, Hi-Speed USB Host and Hi-Speed USB Devices are currently available. DesignWare USB verification IP is currently available to DesignWare Library and DesignWare Verification Library licensees at no additional charge.
About DesignWare Cores
Synopsys DesignWare Cores provide system designers with silicon-proven, digital and mixed-signal connectivity IP for some of the world's most recognized products, including communications processors, routers, switches, game consoles, digital cameras, computers and computer peripherals. Provided as synthesizable RTL source code or in GDS format, these cores enable designers to create innovative, cost-effective systems-on-chips and embedded systems. Synopsys provides flexible licensing options for the DesignWare Cores. Each core can be licensed individually, on a fee-per-project basis or users can opt for the Volume Purchase Agreement, which enables them to license all the cores as part of one simple agreement. For more information on DesignWare IP, visit: http://www.designware.com/ or call 1-877-4BEST-IP
Synopsys, Inc. is a world leader in EDA software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http:/www.synopsys.com.
Forward Looking Statements
This press release contains forward-looking statements within the meaning of the safe harbor provisions of Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected benefits and date of availability of the USB 2.0 design kits for the Chartered and IBM 90-nm common process platform. These statements are based on Synopsys' current expectations and beliefs. Actual results could differ materially from these statements as a result of unforeseen difficulties in completing development of the production-ready versions of the design kits, uncertainties attendant to any new IP offering and the other factors contained in Synopsys' Quarterly Report on Form 10-Q for the fiscal quarter ended January 31, 2004.
NOTE: Synopsys and DesignWare are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Editorial Contacts: Troy Wood Synopsys, Inc. 650-584-5717 Email Contact Julie Crabill Edelman 650-429-2732 Email Contact
Web site: http://www.synopsys.com/