Synopsys Introduces PrimeRail for Power Network Sign-Off

Extending Sign-off in the Galaxy(TM) Design Platform to Voltage-Drop and EM Analysis

MOUNTAIN VIEW, Calif., May 9 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today introduced PrimeRail for power network sign-off. PrimeRail offers new hybrid technology for full-chip static and dynamic voltage-drop and electromigration (EM) analysis. It also builds on Synopsys' silicon-accurate Star-RCXT(TM), HSPICE(R), NanoSim(R) and PrimeTime(R) sign-off technologies to deliver accurate modeling of memories and analog circuits. With the introduction of PrimeRail, the Galaxy Design Platform now provides a comprehensive solution for timing, signal integrity and power network sign-off.

"Today, embedded memory IP contributes up to 70 percent of a chip's area -- and accurate power network sign-off is essential to verify these memories for high reliability and yield," said Alex Shubat, chief technology officer and vice president of research and development at Virage Logic. "We will continue collaborating with Synopsys on our memory verification flow, and will look to standardize on PrimeRail for sign-off of our 90 and 65-nanometer Area, Speed and Power (ASAP) Memory(TM) and Self-Test and Repair (STAR) Memory System(TM) product lines. PrimeRail will help ensure our mutual customers are able to rapidly complete their designs based on Virage Logic's standalone memory products or its IPrima Foundation(TM) semiconductor IP platform offering."

PrimeRail provides sign-off quality results by harnessing the best of Synopsys' core implementation technologies in circuit simulation, parasitic extraction and static timing, coupled with innovations in power network sign- off. Existing solutions perform static voltage-drop analysis alone, or fail to accurately model memories. Moreover, these solutions are not integrated within the implementation platform, leading to a non-convergent flow. PrimeRail's tight integration within the Galaxy Design Platform allows designers to predict voltage drop during floorplanning, perform post-layout static and dynamic analysis with on-chip decoupling capacitance and full-chip sign-off with package parasitics. PrimeRail features the new hybrid technology for highly accurate gate and transistor-level GDSII-based power network sign-off. The hybrid technology simulates arbitrary RLC (resistance-inductance- capacitance) networks enabling sign-off quality dynamic analysis while minimizing memory usage.

"Synopsys continues to lead the industry in sign-off, offering technology innovations for emerging design and silicon requirements," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "We introduced our PrimeTime product for static timing sign-off in 1996, and extended its capabilities to address signal integrity effects with PrimeTime SI in 2001. With the introduction of PrimeRail, we are now enabling PrimeTime customers to address the increasing impact of voltage drop on timing. As a result, the Galaxy Design Platform now offers a comprehensive design sign-off solution that continues to ensure first-pass silicon success."

About Synopsys

Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at .

NOTE: Synopsys, HSPICE, NanoSim and PrimeTime are registered trademarks of Synopsys, Inc., and Galaxy and Star-RCXT are trademarks of Synopsys. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

   Editorial Contacts:
   Nancy Renzullo
   Synopsys, Inc.
Email Contact

   Sarah Seifert
   Edelman Public Relations
Email Contact

CONTACT: Nancy Renzullo of Synopsys, Inc., +1-650-584-1669, or
Email Contact; or Sarah Seifert of Edelman Public Relations,
+1-650-429-2776, or Email Contact, for Synopsys, Inc.

Web site:

Review Article Be the first to review this article
CST: Webinar November 9, 2017


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series

Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise