Synopsys' Distributed Processing and Scalable Architecture Improve Time to Yield While Maintaining Accuracy
"We selected Synopsys' leading-edge DFM tool suite because it provides us with the most scalable and flexible solution available to improve the manufacturing process for both Grace and our customers," said Hao Fan, senior director of TD for Grace Semiconductor. "By using Synopsys' distributed processing architecture we obtained near-linear scalability for OPC conversion. This substantially decreased our turnaround time without sacrificing the accuracy of our designs in silicon."
Grace turned to Synopsys' leading DFM tools to improve the manufacturability of designs. The distributed processing capabilities of Synopsys' tool suite allow Grace to offer its customers fast turnaround time in performing OPC, lithography verification and MDP. As leading-edge chip designs push for higher performance and functionality, the size of GDSII files, and the subsequent runtimes of the DFM tools, are also significantly increasing. Synopsys' Proteus software and SiVL lithography verification tool reduce turnaround time substantially through their ability to simultaneously utilize hundreds of central processing units (CPUs) at once.
"Grace's standardization on Synopsys' DFM tool suite reinforces Synopsys' leadership in the design for manufacturing space," said Edmund Cheng, vice president of Marketing for the Silicon Engineering Group at Synopsys. "Synopsys is committed to delivering best-in-class DFM solutions to companies like Grace to help ensure the manufacturability of the most advanced semiconductor designs and to achieve the fastest time to results."
About Synopsys DFM
Synopsys offers the industry's most comprehensive RTL-to-Mask DFM solution. Its DFM product family addresses critical yield and manufacturability issues with its Proteus mask synthesis, CATS(TM) mask data preparation, SiVL lithography verification, i-Virtual Stepper(TM) mask defect dispositioning, the Taurus(TM) TCAD software products and the recently acquired ISE TCAD platforms. Synopsys leverages this expertise throughout its industry-leading Galaxy(TM) design platform implementation solution in order to help ensure that designs at 90-nm and smaller geometries will meet key manufacturing requirements. Synopsys' DFM product family is the solution-of-choice for yield sensitive, high-value chips, worldwide. Eighty percent of all sub-180-nm microprocessors, 50 percent of all sub-180-nm DRAMs, 80 percent of all sub-180-nm FPGA and graphics chips, 75 percent of all sub-180-nm cellular baseband chips produced use Proteus, and more than 80 percent of all photomasks produced use CATS.
About Grace Semiconductor Manufacturing Corporation
Grace Semiconductor Manufacturing Corporation (Grace) is a pure IC foundry company that specializes in integrated circuit (IC) fabrication. Grace's mission is to become a leading foundry in China by supplying high quality and advanced process technology to domestic and global customers.
Grace is located in Zhangjiang Hi-Tech Park in Pudong, Shanghai, with a total land area of 240,000 square meters and a first-phase investment of $1.63 billion. Two Fabs with one based on 12-inch wafer specifications have been constructed. Currently, Fab 1A (8") is in full production. It already reached a monthly capacity of 27,000 8-inch wafers by the end 2004. More information about Grace is available at http://www.gsmcthw.com/ .
Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ .
NOTE: Synopsys and SiVL are registered trademarks of Synopsys, Inc. CATS, Galaxy, i-Virtual Stepper and Taurus are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
CONTACT: Jennifer Scher of Synopsys, Inc., +1-650-584-5594, or
Email Contact; or Julie Crabill of Edelman, +1-650-429-2732, or
Email Contact, for Synopsys, Inc.; or Angela Chen of Grace
Semiconductor Mfg. Corp, +86-21-51318888-80010, or Email Contact
Web site: http://www.gsmcthw.com/
Web site: http://www.synopsys.com/