NI AWR Software Showcased at NIWeek 2016

EL SEGUNDO, Calif. – July 26, 2016

What:

The latest technologies in  NI AWR Design Environment™ will be showcased during NIWeek 2016 taking place at the Austin Convention Center on August 1-4.  Highlights include:

Academic Pavilion – August 1, 10:00 a.m. – 5:00 p.m.

  • Poster presentation from IMS2016 High-Efficiency Power Amplifier Student Design Contest winners Paolo Enrico de Falco and James Birchall, doctoral students in communications at the University of Bristol, Bristol, UK 

Automated Test Pavilion – August 2-3, 10:00 a.m. – 6:00 p.m. 

  • NI AWR Design Environment’s 5G waveform library as well as system-, circuit- and electromagnetic-level design will be demonstrated 

Improving the  Semiconductor Design-to-Test Flow Panel  – August 2, 10:30 a.m - 11:30 a.m., ACC Meeting Room 2 

  • Experts in chip design, verification and test from Intel, Texas Instruments, Melexis, Cadence Design Systems and National Instruments will present their views on the challenges and potential solutions for improving the overall semiconductor development process.  A question and answer session will follow at the end of the panelists’ presentations. 

Additionally, MaXentric Technologies is an NI Engineering Impact Award Nominee.  MaXentric was nominated for its case study, Design Optimization of Envelope Tracking Power Amplifiers for 5G LTE Using NI Test and Measurement With NI AWR Software, written by lead engineer, Dr. Jonmei "Johana" Yan, lead engineer. The NI Engineering Impact Award dinner and announcement of the winner will be held Tuesday evening, August 2.

For complete details on NI AWR software activities during  NIWeek 2016, visit awrcorp.com/news/events/event/niweek-2016  

Where:

Austin Convention Center, Austin, TX. 

When:

August 1-4, 2016.

 


Contact:

Sherry Hess
Vice President of Marketing, AWR Group, NI
(310) 726-3000
Email Contact




Review Article Be the first to review this article
SI2

AMIQ: dvteclipse

Featured Video
Editorial
Peggy AycinenaIP Showcase
by Peggy Aycinena
Grant Pierce: Grand Challenges in IP
More Editorial  
Jobs
LVS for PDK Design Engineer SILICON VALLEY for EDA Careers at San Jose, CA
LVS PEX DESIGN ENGINEERS SILICON VALLEY for EDA Careers at San Jose, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Upcoming Events
Automotive E/E Architecture China Conference at Shanghai China - May 25 - 26, 2017
EMC PCB Design Integration at 13727 460 Ct SE North Bend WA - Jun 6 - 9, 2017
DAC 2017 Conference at Austin TX - Jun 18 - 22, 2017
2017 FLEX Conference at Monterey Conference Center 1 Portola Plaza, Monterey CA - Jun 19 - 22, 2017
Verific: SystemVerilog & VHDL Parsers
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy