Alma Technologies Releases Encoder IP Core for CCSDS-Developed Lossless and Lossy Image Data Compression

TOULOUSE SPACE SHOW, TOULOUSE, France, June 28, 2016 — (PRNewswire) —  Alma Technologies S.A., a company that designs, markets, sells and supports innovative semiconductor IP since 2001, today introduced at the Toulouse Space Show 2016 a new encoder IP core which implements the CCSDS 122.0-B-1 lossless and lossy image data compression standard.

Alma Technologies today introduced at the Toulouse Space Show 2016 a new encoder IP core which implements the CCSDS 122.0-B-1 lossless and lossy image data compression standard.

The CCSDS 122.0-B-1 specification is part of a standards suite developed by the Consultative Committee for Space Data Systems. The CCSDS is formed by the major space agencies of the world for the development of communications and data systems standards for space applications. The CCSDS 122.0-B-1 fits the compression requirement for a wide range of spaceborne two-dimensional spatial image data. In these applications the requirement is for a scalable data reduction, with the option to use lossless or lossy compression, using a memory-efficient and reduced complexity algorithm that results in a fast, low-power and compact hardware implementation.

The new Alma Technologies CCSDS-122-E encoder IP core is an advanced implementation of the CCSDS 122.0-B-1 image data compression standard and supports image or video data with a pixel dynamic range of up to 16 bits. The CCSDS-122-E is a complete and autonomous CPU/GPU-less encoder. It accepts the uncompressed image data in standard raster scan pixel order and outputs standalone and fully compliant CCSDS 122.0-B-1 byte-stream format. The CCSDS-122-E is designed for enabling high-rate data compression, with low resource usage, in both FPGA and ASIC implementations.

Similar to JPEG 2000, the CCSDS 122.0-B-1 utilizes a two-dimensional Discrete Wavelet Transform (DWT) for image data decorrelation. CCSDS 122.0-B-1 uses a 9/7 integer DWT for the lossless compression, while a 9/7 float DWT is also specified for improved lossy compression efficiency, especially at low bit-rates. Both DWT options are available by the Alma Technologies CCSDS-122-E encoder. For complete control by the application of the lossy compression ratio, the CCSDS-122-E includes also the optional rate control functionality that is provisioned by the standard.

The CCSDS 122.0-B-1 standard was developed to balance between compression performance and complexity with particular emphasis on spacecraft applications. Compared to JPEG 2000, it achieves slightly lower, but essentially similar, lossless and lossy compression efficiency. Due to its reduced complexity, it requires significantly less silicon logic area, along with reduced amount of internal memories, and achieves higher throughput. The Alma Technologies CCSDS-122-E encoder realizes all these expected benefits, while also not needing an external memory device for its implementation.

Contact us online at, or call us at +30-210-603-9850 to learn more.

About Alma Technologies

Alma Technologies is a semiconductor IP provider, designing high-quality FPGA and ASIC IP cores since 2001. Its products stand out for their engineering, being complete, easy-to-use and reliable IP solutions. World-class technical support and a long track record of proven designs by more than 200 licensees in over 20 countries provide Alma Technologies customers with excellent service and great value.

Available either as self-contained and implementation technology independent VHDL or Verilog RTL, or as optimized Netlists for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices, Alma Technologies IP ensures a fast and trouble-free integration in any FPGA or ASIC design. Learn more at:


Photo -

Logo -

Contact: Vassilis Spiliotopoulos, Email Contact, +30-210-603-9850 ext.107

To view the original version on PR Newswire, visit:

SOURCE Alma Technologies S.A.

Alma Technologies S.A.

Review Article Be the first to review this article


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Acquiring Mentor: Four Good Ideas, One Great
More Editorial  
SENIOR ASIC Design Engineer for TiBit Communications at Petaluma, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Sr. staff ASIC Design Engineer -2433 for Microchip at San Jose, CA
Upcoming Events
DeviceWerx - 2016 at Green Valley Ranch Casino & Resort Las Vegas NV - Nov 3 - 4, 2016
2016 International Conference On Computer Aided Design at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
ICCAD 2016, Nov 7-10, 2016 at Doubletree Hotel in Austin, TX at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
Electric&Hybrid Aerospace Technology Symposium 2016 at Conference Centre East. Koelnmesse (East Entrance) Messeplatz 1 Cologne Germany - Nov 9 - 10, 2016
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy