Renesas Electronics Develops Two-Port On-Chip SRAM Specialized in Improving Video Processing Performance of Vehicles for the Autonomous-Driving Era

Combines High Integration of 6.05 Mb/mm2 (1.8× Previous Level) and 313-Picosecond Fast Read Operation

TOKYO — (BUSINESS WIRE) — June 16, 2016 — Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today announced the successful development of a new two-port on-chip Static Random Access Memory (SRAM) for use in system-on-chips (SoCs) for in-vehicle infotainment systems. The new on-chip SRAM will be used as video processing buffer memory in high-performance SoCs that will play an important role in making the autonomous-driving vehicles of the future safer and more reliable. The new SRAM is optimized for parallel processing of video data and will enable sophisticated video data processing such as obstacle recognition utilizing real-time processing of high-resolution vehicle camera videos and augmented reality (AR) display on the windshield. In prototypes fabricated using a cutting-edge 16-nanometer (nm) process, the new SRAM achieved a fast read access time of 313 picoseconds (ps) at the low voltage of 0.8 V. Single-port SRAM cells are used to implement two-port SRAM functionality that allows independent read and write operations, making it possible to achieve fast read access alongside power efficiency and compact chip size.

Recently, advanced driver assistance systems (ADAS) such as automatic braking employing radar or other sensors have become widespread, and the development of technology oriented toward the autonomous-driving vehicles of the future has advanced rapidly. Technology that uses video data from vehicle cameras to recognize the peripheral environment and the driver in order to provide accurate information to the driver has grown in importance. One way to boost video data processing performance is to use algorithms that divide up each video data into small sections for parallel processing. By optimizing the video processing buffer memory for such algorithms it is possible to achieve faster video data recognition, processing, and display.

Previously, Renesas has developed two types of on-chip SRAM with a 16nm FinFET structure: (1) single-port SRAM allowing either read or write access at any one time and (2) dual-port SRAM allowing simultaneous read and write operations. Both types have been used in Renesas’ R-Car SoCs for in-vehicle infotainment systems. Now, with practical usability in mind, Renesas has developed a double-pumping circuit technology using single-port SRAM cells that allows independent read and write operations, to realize reduced power consumption, enhanced operating margin at lower voltage, and more compact memory area on the chip while maintaining fast read access. In addition, the development of a low-power circuit using a FinFET structure effectively reduces leakage power to approximately one-half the previous level during the standby mode.

Key features of the newly-developed SRAM technology:

(1) Adoption of new double-pumping circuit technology to achieve: two-port SRAM functionality allowing independent read and write operations using single-port SRAM cells; high integration of 6.05 Mb/mm2 (1.8× previous level); and 313-ps fast read access time

A large amount of SRAM configured as high-performance internal buffer memory is essential for fast and accurate processing of video data. To boost video data processing performance it is necessary not only to increase the operation speed of the SRAM, but also to enable multi-port operation allowing simultaneous read and write accesses, which fetch video processing data for operations and store the data after operations finish.

Previously, Renesas used dedicated multi-port memory cells when at the same time developing SRAM for highly accurate and faster video data processing. However, since more elements are needed than with ordinary single-port memory cells, there were challenges with increased on-chip area and power leakage. It was also necessary to provide sufficient operating margin to accommodate simultaneous accesses to memory cells, and this caused problems such as reduced speed and worsening of the operating voltage lower margin characteristics.

Renesas has developed a SRAM macro using conventional single-port SRAM cells that implements the newly-developed double-pumping circuit technology to enable simultaneous read and write operations in a single clock cycle. Specifically, two sequential clock cycles, a read cycle and a write cycle, are generated internally by the macro. Within a single external cycle the read operation occurs first, followed by the write operation in the second part of the cycle. The peripheral circuits are optimized so that the internal timing to support this is generated automatically. The read operations are identical to those when conventional single-port SRAM is used. Therefore, there is no need for the countermeasures against disturb issues at the simultaneous access required with multi-port cells, which enables faster read speeds. In prototypes fabricated using a cutting-edge 16 nm process, the new SRAM delivered faster and stable operation at 313 ps at the low voltage of 0.8 V. Also, thanks to the compact single-port SRAM cells used, high integration of 6.05 Mb/mm2 1.8 times that of conventional dual-port SRAM, was achieved. Thus, it is possible to provide improved parallel video data processing while at the same time meeting growing demand for larger-capacity and faster on-chip SRAM.

(2) Circuit design that leverages the advantages of FinFET to achieve low power consumption

As semiconductor fabrication processes become more ultrafine and supply voltages drop, leakage current tends to increase due to the lower threshold values of the device elements. This can result in a vicious cycle in which heat generation from increased power during standby at room temperature or operating power during processing operation causes the leakage current to increase, which in turn further raises the temperature and causes even more leakage current. Switching from the planar transistor structure used with the earlier 28nm process to a 16nm FinFET structure provides improved transistor on-off characteristics while also changing the leakage current thermal characteristics and the voltage dependency. With the 28nm process it was possible to reduce leakage current by lowering the voltage, however since the FinFET is less voltage-dependent, lowering the voltage produced lower-than-expected reduction in leakage power than anticipated. Instead, Renesas has therefore developed a low-leakage circuitry that applies bias to the source line potential of the new SRAM cells. It effectively reduces leakage power while being relatively unaffected by thermal characteristics or process corner inconsistency. It has been confirmed that the new circuit technology, when used as two-port SRAM for 3D video processing applications, reduces power consumption roughly to half in comparison with earlier circuit configurations.

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