Toshiba's Electrostatic Discharge (ESD) Protection Device with 0.13μm Process for Analog Power Semiconductor Improves ESD Characteristics

TOKYO — (BUSINESS WIRE) — June 15, 2016Toshiba Corporation (TOKYO:6502) has developed an electrostatic discharge (ESD) protection device for analog power semiconductor application, fabricated with advanced 0.13μm process technology, that optimizes the structure of transistor and significantly improves ESD characteristics. ESD protection is much more robust, up four times, and the standard deviation is only 1/12 that of the conventional structure. Analysis of 3D simulations has also allowed Toshiba to identify a mechanism for optimizing transistor structure to boost ESD robustness. Toshiba announced these advances at “ISPSD2016”, the international semiconductor symposium held in Czech on June 14, 2016.

This Smart News Release features multimedia. View the full release here:

Schematic cross-section of studied structure (Graphic: Business Wire)

Schematic cross-section of studied structure (Graphic: Business Wire)

Injections of ESD surges, whether from the human body or equipment, have the potential to destroy semiconductor devices, as ESD current flows cause local temperature increases inside silicon. ESD protection devices are required to protect internal circuit. This is especially true for analog power semiconductor devices required to apply 10V to 100V, which need a high rated voltage. In this case, ESD protection devices must ensure high current flow, which results in enlarged chip size. Shrinking the size of the ESD protection device is an issue in realizing more compact chips.

Using 3D simulation analysis of an ESD event, Toshiba found out that ESD induced destruction is caused by lattice temperature increase due to the current flowing at the highest electric field point. Modifying the transistor structure, which extending the drain low resistive region to the source direction and suppressing the lateral silicon resistance, shifts the current flow from the bottom of the drain to source direction and detaches it from the highest electrical field point. This optimized design was found to increase ESD robustness by up to four times and to decrease the standard deviation down to 1/12. In addition, the device size required to ensure HBM* ±2000V was cut by 68%.

Toshiba offers advanced analog process platforms, with 0.13μm process technology, that can be embedded with the transistors such as CMOS, DMOS, bipolar transistor and the passive devices such as resistor and capacitor. User can select a process suited to each application from three process platforms: “BiCD-0.13” is mainly for automotive (DMOS line up is up to 100V); “CD-0.13BL” is mainly for motor control drivers (DMOS line up is up to 60V); and “CD-0.13” process is mainly for power management IC (DMOS line up is up to 40V).

Toshiba plans to release products using the CD-0.13 process applied in this technology in 2017 and proactively continue to implement to other process platforms to improve electrostatic discharge characteristics.

* HBM (Human Body Model) : one of the parameter to indicate ESD robustness

About Toshiba

Toshiba Corporation, a Fortune Global 500 company, channels world-class capabilities in advanced electronic and electrical product and systems into three focus business fields: Energy that sustains everyday life, that is cleaner and safer; Infrastructure that sustains quality of life; and Storage that sustains the advanced information society. Guided by the principles of The Basic Commitment of the Toshiba Group, “Committed to People, Committed to the Future”, Toshiba promotes global operations and is contributing to the realization of a world where generations to come can live better lives.

Founded in Tokyo in 1875, today’s Toshiba is at the heart of a global network of 550 consolidated companies employing 188,000 people worldwide, with annual sales surpassing 5.6 trillion yen (US$50 billion). (As of March 31, 2016.)
To find out more about Toshiba, visit


Toshiba Corporation
Storage & Electronic Devices Solutions Company
Koichi Tanaka / Kota Yamaji, +81-3-3457-3576
Communication IR Promotion Group
Business Planning Division
Email Contact

Review Article Be the first to review this article


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Acquiring Mentor: Four Good Ideas, One Great
More Editorial  
SENIOR ASIC Design Engineer for TiBit Communications at Petaluma, CA
Sr. staff ASIC Design Engineer -2433 for Microchip at San Jose, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Upcoming Events
DeviceWerx - 2016 at Green Valley Ranch Casino & Resort Las Vegas NV - Nov 3 - 4, 2016
2016 International Conference On Computer Aided Design at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
ICCAD 2016, Nov 7-10, 2016 at Doubletree Hotel in Austin, TX at Doubletree Hotel Austin TX - Nov 7 - 10, 2016
Electric&Hybrid Aerospace Technology Symposium 2016 at Conference Centre East. Koelnmesse (East Entrance) Messeplatz 1 Cologne Germany - Nov 9 - 10, 2016
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy