Design Verification Challenges in Modern SoCs - HDL Design House Webinar

Igor Ikodinovic, HDL Design House's Principal Project Manager will host an online event about various issues that arise in today's SoC design verification and how to solve them efficiently and effectively.

Belgrade, Serbia - May 31st, 2016 - HDL Design House, provider of digital, analog, and back-end design and verification services and products in numerous areas of SoC, will host a webinar to be presented by Mr Igor Ikodinovic, Principal Project Manager, who will discuss how different standard as well as numerous non-standard verification challenges are dealt with in practice by HDL Design House.

Modern SoCs contain a large number of digital and analog modules whose functionality needs to be verified at the system (top) level. A number of different problems arise in this process, including how to choose the verification methodology, language and implementation platform, how to create proper test plans, how to ensure functional coverage conversion, how to perform verification using different power modes, and more.

Beside these standard verification problems, the list often includes non-standard problems such as how to properly model analog modules in the SoC verification environment, how to model system performance and verify that system performance goals are met, improving the workflow or tools used, and others. The webinar will outline a practical approach to resolving these issues.

This online event will include topics such as advantages of coverage-driven constrained-random verification methodology, UVM-based SoC functional verification flow, creating test plans and ensuring coverage conversion, challenges of SoC performance verification, and verification of analog blocks in SoC design verification environment.

The webinar is taking place on Thursday 16 June, 10 am PST and is free to attend. Joining instructions are available on the webinar registration page on HDL Design House website:  www.hdl-dh.com/webinar.html




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