On panel: “How Do We Make IP Reuse Work?”
Demonstrating SoC Design and IP Management Platform
FREMONT, Calif., May 24, 2016 – At DAC 2016, ClioSoft, the pioneer and leading developer of system-on-chip (SoC) design configuration and enterprise intellectual property (IP) management solutions for the semiconductor industry, will demonstrate the SOS Design Management Platform and IP Management solutions as well as participating on a panel in the IP Track. SOS is the EDA industry’s most widely installed design data and enterprise IP management solution for analog, RF, digital and mixed-signal designs. ClioSoft’s SOS platform is integrated with major EDA flows from Cadence Design Systems, Keysight Technologies, Mentor Graphics and Synopsys.
The 53rd DAC will be held this year from June 5 to June 9 in the Austin Convention Center in Austin, Texas.
How Do We Make IP Reuse Work? Moderated by Brian Fuller, editor-in-chief, ARM, Inc.
ABSTRACT: The plug-and-play concept of using IP to create SoCs has not taken off as expected. Representatives from the design, provider and semiconductor communities will discuss the challenges that have to be overcome and what can be done to improve IP reuse for analog and digital designs. Will emerging technologies such as 3D stacking help? What is happening with new languages and proposed standards? Will an IP management system that lets designers find the right existing IP and track its previous success help?
Representatives from the design, provider and semiconductor communities will discuss what ails the IP industry and what can be done to improve IP reuse for analog and digital design. For more detail, see http://www2.dac.com/events/eventdetails.aspx?id=200-59
Ranit Adhikary - ClioSoft, Inc., Fremont, CA
Lisa Minwell - eSilicon Corp., San Jose, CA
Rwik Sengupta - Samsung Semiconductor, Inc., Austin, TX
John Koeter - Synopsys, Inc., Austin, TX
WHEN: 3:30 to 4:30 pm on Wednesday, June 8, 2106
WHERE: Room 18AB, Austin Convention Center
SOS Design Management Platform from ClioSoft is integrated with tools from all major EDA vendors, providing the only cohesive design environment for all types of digital, analog, RF and mixed-signal designs. SOS facilitates multi-site design collaboration and includes, among other features, integrated revision control, release and derivative management and interfaces to commonly-used bug tracking systems. Tool flows into which SOS is integrated include those from Cadence Design Systems®, Keysight Technologies, Mentor Graphics and Synopsys®.
At DAC 2016, ClioSoft will showcase how the tight coupling of SOS with major design flows empowers design engineers to manage their design data directly from their familiar design cockpit. This enables design teams to be productive and efficient while reducing the possibility of design re-spins due to incorrect configurations.
Visual Design Diff (VDD) from ClioSoft enables users to quickly compare design differences in schematics, layout and RTL by graphically highlighting the differences. A hierarchical diff option allows all differences for the entire design hierarchy below the selected view to be flagged.
IP Management from ClioSoft helps accelerate SoC development by managing internal and third-party IPs. It eases the pains associated with creating IPs, determining IP suitability and tracking the IPs across an enterprise.
WHEN: 10:00am to 6:00pm from Monday, June 6 to Wednesday, June 8, 2016. Register to arrange a private demonstration of their products.
WHO: Of interest to analog/mixed-signal, RF and digital designers and CAD engineers/ managers.
WHERE: Booth #519, Austin Convention Center
ClioSoft is the pioneer and leading developer of system-on-chip (SoC) design configuration and enterprise IP management solutions for the semiconductor industry. The company’s SOS Design Collaboration Platform, built exclusively to meet the demanding requirements of SoC designs, empowers multi-site design teams to collaborate efficiently on complex analog, digital, RF and mixed-signal designs. ClioSoft’s collaborative IP management solution improves design reuse by providing an easy-to-use workflow as well as management of the process of shopping, consuming and producing new IPs. Designers can very easily browse the different versions of existing IPs and their derivatives, and review the lineage, IP licensing, security, issue and defect tracking with remarkable ease to determine their suitability before using them in their designs.
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