Intilop delivers a Network Security TOE Module for Altera and Xilinx FPGAs for their 10G & 40G Full TCP & UDP Accelerators to a major government client

Intilop's 40G accelerator was demoed with Altera in November at Supercomputing 2015 in Austin, TX.

MILPITAS, Calif., May 20, 2016 — (PRNewswire) — Intilop, Inc., a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol Accelerators like Full TCP, UDP, IGMP & other Mega IP Cores, Systems and Solutions since 2009, delivers yet another industry first: a full TCP and UDP Accelerator with Network Security capability which performs functions of firewall and other monitoring functions at full line rate. In addition to full TCP/UDP offloading, this security module performs port filtering, blocking, monitoring and related functions in FPGA hardware thereby relieving CPU from these tasks. They are performed in nanosecond speeds and with ultra precision. The fact that CPU which gets bogged down under high traffic rates and sometimes missing some events, can be used for other application functions. So this is a win-win situation for both.

Ultra-fast and precise processing time of around 100 nanoseconds for this module including TCP and UDP with thousands of sessions initially at 10G, sets the bar much higher for speed and performance powered by a 7+ year mature and proven TCP Protocol Compliant architecture. The Security module for their latest 40G TOE is planned for Q3 2016

It was a highly significant achievement to develop this cutting edge technology rich architecture which implements Network Security module coupled with TCP and UDP Accelerators running at Full 10G Line rate. 40G soon to be released. The 10G TOE has been in volume production for more than 5 years now and is deployed around the globe.

Working out of the box solutions with Choice of Cores implementing and this security module with 1K, 512, 256, 128, 32 and fewer concurrent TCP/UDP Sessions will be available in Q3 2016.

A sample of their TCP and UDP Accelerators can be found also at Altera and Xilinx websites:

Altera: https://www.altera.com/solutions/partners/ip-partners/intilop.html

Xilinx:  http://www.xilinx.com/esp/datacenter/data_center_ip.html

Xilinx: http://www.xilinx.com/esp/datacenter/data_center_ip.html

It not only offers ~100 ns latency and wire speed TCP performance, it also offers customization flexibility to network architects to design world-class system-level applications tailored to their specific needs.

The TOE's architecture is highly scalable, customizable and adaptable without compromising on low latency or performance. Intilop's product-line solutions are available in flexible FPGA/ASIC/SoC technologies which can easily accommodate diverse set of appliance maker's technical design specifications.

As a pioneer, Intilop was the first company to deliver a series of Full TCP Offload Engines on FPGAs in 2009. Their sub 100 ns latency MAC+TOE&UOE are considered a 'Gold Standard' by the industry experts.
The latency barrier of 100 nanoseconds and throughput of more than 1 G byte/s per port had been set by them since their first 10G Series of TCP engines in 2011.

About IntilopWebsite: www.intilop.com   
Intilop is a developer and pioneer in advanced networking silicon IP and system solutions, custom hardware solutions, SoC/ASIC/FPGA integrator and total system solutions provider for Networking, Network Security, storage and Embedded Systems. They offer silicon proven semiconductor IPs with comprehensive hardware and software solutions.

Pricing and product info contact: Email Contact   Email Contact Address:
Intilop Corporation. 830 N Hillview Drive. Milpitas, CA 95035.  PH: 408-791-6700

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/intilop-delivers-a-network-security-toe-module-for-altera-and-xilinx-fpgas-for-their-10g--40g-full-tcp--udp-accelerators-to-a-major-government-client-300272591.html

SOURCE Intilop, Inc.

Contact:
Intilop, Inc.
Web: http://www.intilop.com




Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Job Openings: Can EDA Predict the Future
More Editorial  
Jobs
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Technical Support Engineer Germany/UK for EDA Careers at San Jose, CA
Engr, Elec Des 2 for KLA-Tencor at Milpitas, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Verification Engineer for Ambarella at Santa Clara, CA
ASIC Design Engineer for Ambarella at Santa Clara, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy