Aldec Extends Spectrum of Verification Tools for Use in Digital ASIC Designs

HENDERSON, Nev. — (BUSINESS WIRE) — May 17, 2016Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for digital system designs, today announces that its verification tools suite, honed over 30 years of complex FPGA design verification, is available for ASIC chip design.

Covering the full digital verification flow from design and test planning through simulation, emulation, and prototyping, Aldec’s popular verification tools help designers in small and large fabless companies ensure that complex digital ASIC designs meet all functional and timing requirements before being committed to a mask set, helping to protect against the high cost of a mask respin.

Aldec’s verification suite includes cost-effective, high-performance tools for HDL verification across the full range of industries, including computing, storage, communications, and the Internet of Things, as well as safety-critical applications within aerospace, medical, automotive, and industrial systems.

“Engineers need a reliable verification partner that suits their budgets while still providing a high level of support,” said Dr. Stanley Hyduke, Aldec Founder and CEO. “To fill this need, we at Aldec have extended our spectrum of verification tools for use in digital ASIC designs.”

Aldec tools support all phases of the digital flow, from design planning through to prototyping for software verification.

  • Spec-TRACER™  manages requirements/specifications, providing capture, mapping to tests, and full traceability for compliance with critical-systems standards like ISO-26262 for automotive, IEC-61508 for industrial and DO-254 for avionics.
  • ALINT-PRO™provides VHDL and Verilog code analysis (linting) as well as clock-domain-crossing (CDC) verification. Aldec’s libraries contain well-established criteria for basic coding, CDC, DO-254, STARC, and RMM standards.
  • Aldec’s high-performance Riviera-PRO™ simulator speeds verification through both fast incremental compilation and fast multi-core simulation execution. It accepts code written in VHDL, Verilog, SystemVerilog, SystemC, and mixtures of these languages. It supports the latest verification libraries, such as OVM/UVM, along with many specialized graphical UVM debugging tools. It offers code and functional coverage capabilities with coverage analysis tools to support a metric-driven verification approach. It can handle the multi-million-gate designs typical of ASIC projects.
  • The HES-7™ board and HES-DVM™ software combine to provide a hardware emulator with a SCE-MI 2 interface. Aldec hardware debugging provides 100% visibility into the design at the RTL level. HES-DVM manages design setup, design compiler integration, and debug instrumentation. It partitions large designs across multiple HES-7 boards and supports several host communication schemes for different emulation modes:
    • PLI/VHPI for bit-level acceleration
    • SCE-MI 2 and DPI-C for function-based transaction-level and UVM verification
    • SCE-MI 2 and TLM for macro-based hybrid emulation with a virtual platform running processor models or a SystemC testbench
    • In-circuit emulation with speed adapters for external data streams and interfaces
  • The CTS™ platform enables at-speed module execution for catching bugs that are evident only at high speeds.
  • The HES-7™ boards give software programmers a hardware prototype for high-speed testing of software against the hardware design.
  • The verification tools are supported by a broad set of verification IP ( VIP ) libraries that save time and effort while ensuring thorough design checkout.

Aldec’s ASIC verification tool suite is available today. For more information on Aldec’s ASIC tool flow visit www.aldec.com/products . To evaluate, email Email Contact or call +1 (702) 990-4400 or contact an Aldec worldwide distribution partner .

About Aldec

Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com



Contact:

Aldec, Inc.
Christina Toole,
702-990-4400
Email Contact




Review Article Be the first to review this article
CST: Webinar November 9, 2017

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise