Faraday Reduces Packaging Design Time by 60 Percent Using Cadence OrbitIO Interconnect Designer and SiP Layout

OrbitIO interconnect designer capabilities deliver hierarchical multi-substrate-optimized design for SoCs and ASICs across IC package/SiP and systems

SAN JOSE, Calif., May 4, 2016 — (PRNewswire) — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Faraday Technology Corporation, a leading fabless ASIC/SoC and IP provider, used Cadence® OrbitIO™ interconnect designer and Cadence SiP Layout to reduce their packaging design time by 60 percent over their previous methodology.

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OrbitIO and SiP Layout enable automated IC/package/PCB interconnect design and optimization. This capability can better optimize the interconnect pathways for routing and signal/power integrity performance as compared to the current methods of using static spreadsheets. The multi-substrate interconnect pathway design optimizes design performance and minimizes substrate complexity and cost by allowing tradeoff exploration and decisions early in the process. By implementing this process, Cadence is able to reduce the typical spreadsheet-based bump/ball map planning studies from days/weeks with multiple iterations to just a few hours with little to no iterations using the single multi-fabric environment of the OrbitIO interconnect designer. For more information on Cadence OrbitIO interconnect designer and Cadence SiP Layout, visit www.cadence.com/news/Faraday.

"Die bump planning and optimization is a critical part of our SoC and ASIC design process in order to meet our performance goals," said Jim Wang, senior associate vice president of Faraday. "Using OrbitIO helps us achieve our goals in an efficient manner and enabled us to reduce design time by up to 60 percent, while delivering the quality of results our customers expect."

"With our customers' needs as top priority, we enhanced the OrbitIO Interconnect Designer, which contributed to a fully automated methodology for optimizing cross-domain interconnect pathways," said Saugat Sen, vice president of R&D, PCB and IC Packaging Group at Cadence. "The result is a streamlined design flow that leads to reduced design cycles and lower product development costs."

About Faraday Technology Corporation
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDR2/3/4, low-power DDR1/2/3, MIPI, V-by-One, MPEG4, H.264, USB 2.0/3.1 Gen 1, 10/100/1000 Ethernet, Serial ATA, PCI Express, and programmable SerDes, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. Faraday is listed on the Taiwan Stock Exchange, ticker 3035. For more information, please visit:  www.faraday-tech.com 

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and OrbitIO is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/faraday-reduces-packaging-design-time-by-60-percent-using-cadence-orbitio--interconnect-designer-and-sip-layout-300262506.html

SOURCE Cadence Design Systems, Inc.

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