eMemory Launches Enhanced NeoFuse IP for IoT Applications

Hsinchu, Taiwan, Apr. 07, 2016 – eMemory announces today that its enhanced version of NeoFuse IP has been verified in the 55nm ultra-low-power (ULP) process and is currently being delivered to customers to design-in for risk production. The features such as low supply voltage operation, compact IP area, and an internal charge pumping circuit are expected to facilitate flexible circuit design, enhance chip integration, and optimize power efficiency in battery-operated devices and IoT-related applications. These unique features also create a secure environment for connected devices in which NeoFuse IP offers the functionality of security key setting and random seed generation. 

The enhanced version of NeoFuse IP in the 55nm ULP process will support 0.9V ultra-low voltage operation, and this paves the way for early readiness for data and setting in chip operation. Moreover, this solution is able to embed the charge pumping circuit to write data in programming mode with insignificant area extension, thus no need to consider high voltage supply, will enable IC design teams to simplify the adoption of embedded NVM solutions and shorten the time to market. 

Chris Lu, eMemory Vice President of OTP Business Group, says, “In addition to low power consumption, more and more IP users who are interested in ULP process platforms request low supply voltage operation and compact IP area with simple power supply. That’s why eMemory is offering the enhanced version of NeoFuse IP in the 55nm ULP process, a NeoFuse-qualified platform, to expand the usage of eMemory’s solution. The enhanced version will be rolled out on other ULP process platforms successively.” 

To fulfill the requirements for the devices in IoT related applications, the demands for embedded logic NVM solutions in ULP process nodes is moving towards a wider voltage range and more built-in functions with smaller IP area. Targeting these market requirements, eMemory will offer more platforms for enhanced versions of NeoFuse IP in IoT-related applications. 

About eMemory

eMemory (Stock Code: 3529) is a global leader in logic process embedded non-volatile memory (eNVM) silicon IP. Since it was established in 2000, eMemory has devoted itself to research and development of innovative technologies, offering the industry’s most comprehensive platforms of patented eNVM IP solutions, including NeoBit (OTP Silicon IP), NeoFuse (Anti-Fuse OTP Silicon IP), NeoMTP (1,000+ Times Programmable Silicon IP), NeoFlash (10,000+ Times Programmable Silicon IP), and NeoEE (100,000+ Times Programmable Silicon IP), which are supplied to semiconductor foundries, integrated devices manufacturers (IDMs), and fabless design houses worldwide. eMemory’s eNVM silicon IPs support a wide range of applications, including trimming, function selection, code storage, parameter setting, encryption, and identification setting. The company has the world’s largest NVM engineering team and prides itself on providing partners with a full-service solution that sees the integration of eMemory eNVM IP from initial design stages through fabrication. For more information about eMemory, please visit www.ememory.com.tw

 

Contact:

eMemory Technology Inc.
Public Relations Department
Michelle Wang
Phone: +886-3-5601168 #1121
Email: Email Contact




Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Upcoming Events
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise