elitePLUS semiconductor Technologies released a fully functional 400G PCS VIP

Bangalore - elitePLUS semiconductor Technologies, today released a fully functional 400G PCS VIP, which is verified against an IP supplied by one of the major Ethernet System Supplier. The 400G VIP is fully compliant to the latest IEEE 802.3bs (public area) specification and is written in System Verilog and UVM1.x methodology standards. The ELITE_PCS_400G VIP is packaged with source code, compliance test Cases, functional coverage and many features.

ELITE_PCS_400G Verification IP provides a smart and effective way to verify PCS Features with 400G Speed features. The Verification IP is fully compliant with the latest PCS and Ethernet standard specifications and provides the following features.

Some of the feature highlights:

VIP support and configuration:
  •  IEEE 802.3bs (public area) 400Gbps Ethernet compliant.
  •  Configurable SERDES bus width.
  •  FEC Encoder/Decoder (RS) – New architecture.
  •  Protocol checker.
  •  Coverage.
VIP controls:
  •  64B/66B Encoder Error insertion.
  •  Transcode Error insertion.
  •  Scrambler bypass support.
  •  Parameterized AM values.
  •  Parameterized AM repetition.
  •  FEC error insertion (Controlled and Random).
  •  Skew insertion.
  •  Configurable SERDES bus width. Gearbox width 40 & 64 bit.

About elitePLUS 

elitePLUS Semiconductor Technologies is an IP and Design services company established in 2014, with technical expertise in providing high quality and dependable services in Digital, Analog and Mixed Signal areas. 

We offer a spectrum of design and verification services, which includes defining specification, logic partitioning, micro-architecture, RTL coding, synthesis, developing custom and standard VIPs and verification environment development using both traditional and advanced techniques. 

Our ace team of engineers and consultants are skilled across a wide range of the most powerful modern tools, technologies and methods. We are experienced professionals in making best practices fit into existing flow and have to our credit several FIRST-PASS Silicon successes. 




Review Article Be the first to review this article
CST: Webinar November 9, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise