Arasan Announces USB 2.0 PHY in Ultra Low Power TSMC 40LP

San Jose, CA. -  Arasan’s USB 2.0 PHY has been designed to target mobile devices and the automotive market. This IP expands Arasan’s library of nodes, now available from 180nm to 28nm from major foundries including automotive grade qualifications. Ubiquitous in PCs, USB 2.0 is now the charging and media transport interface for billions of mobile products from Smartphones to headphones. USB is pervasive in all electronic segments including automotive, enterprise, medical and industrial applications.

Arasan entered the USB 2.0 PHY IP market with the acquisition of the silicon-proven Mentor technology. Arasan engineering successfully integrated the technology into Arasan’s design flow to ensure interoperability with its controllers. Arasan is the only company to offer the complete suite of USB 2.0 IP products including the USB 2.0 Host, Hub, Device, OTG, and PHY. Arasan also offers the HSIC option for chip to chip connections over USB.

“With 20 years of USB experience and over 100 USB Semiconductor Licensees, Arasan is the Total USB IP Solution provider”, Chari Santhanam, Arasan VP. of Engineering and a recognized expert on USB IP.


Arasan’s USB 2.0 IP PHY and USB 2.0 controller IP are available for immediate delivery. Contact for more information.

About Arasan

Arasan Chip Systems is a leading provider of Total IP Solutions for mobile and the next generation of Smart applications from home to automobile. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for Ethernet, MIPI, PCIe, USB, UFS, SD, SDIO, eMMC, and UFS. Arasan’s Total IP products serve system architects and chip design teams in applications that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.

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