Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow

Cadence technology enables Silicon Labs to accelerate delivery of energy-efficient Blue Gecko Bluetooth Smart SoCs to the IoT market

SAN JOSE, Calif., Feb. 24, 2016 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Silicon Labs ( used a Cadence® mixed-signal low-power flow to reduce overall design time, significantly speeding time to market. Silicon Labs adopted the flow for its new Blue Gecko family of wireless system-on-chip (SoC) devices ( that provide ultra-low-power Bluetooth Smart connectivity for Internet of Things (IoT) applications.

Cadence Logo.

For design, Silicon Labs used the comprehensive Cadence mixed-signal, low-power flow based on the unified OpenAccess (OA)-enabled Incremental Technology Database (ITDB) to seamlessly interoperate between the Cadence Virtuoso® analog platform and the Cadence digital implementation suite of tools. For mixed-signal verification, Silicon Labs adopted the Cadence Spectre® Multi-Mode Simulation (MMSIM) solution, which improved productivity by up to 3X, helped reduce power consumption and extended the connectivity range of the Blue Gecko SoCs with high performance. The mixed-mode, full-chip functional simulation enabled by Incisive® Enterprise Simulator with its DMS Option accelerated Silicon Labs' design verification by up to 10X, compared to transistor- or device-level simulation options.

For more information on the Cadence mixed-signal low-power flow, please visit

"Providing our IoT customers with the highest power output at the highest energy efficiency in a cost-effective manner is integral to the success of our wireless SoC products," said James Stansberry, senior vice president and general manager of Internet of Things products at Silicon Labs. "Silicon Labs' new Blue Gecko family of wireless SoC devices is designed to provide the performance, energy efficiency, security and design simplicity that Bluetooth Smart applications require, and the Cadence mixed-signal low-power flow helped us achieve our SoC product development and time-to-market goals."

Silicon Labs used the Cadence Virtuoso analog platform, which included the Virtuoso Schematic Editor, the Virtuoso Analog Design Environment and the Virtuoso Layout Suite. The digital implementation suite consisted of the Innovus™ Implementation System, the Genus™ Synthesis Solution and Conformal® Low Power. The flow also incorporated Cadence signoff solutionsthe Tempus™ Timing Signoff Solution, the Quantus™ QRC Extraction Solution, the Voltus™ IC Power Integrity Solution and the Voltus-Fi Custom Power Integrity Solutionto ensure first-pass silicon.

The Spectre MMSIM solution used by Silicon Labs consisted of the Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), Spectre RF Option and Virtuoso AMS Designer tool suites that provide comprehensive analog, RF and mixed-signal simulation capabilities to consistently, accurately and quickly design, verify and characterize complex wireless SoCs at both the block and chip levels.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Conformal, Incisive, Spectre and Virtuoso are registered trademarks and Genus, Innovus, Quantus, Tempus and Voltus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
Email Contact

Logo -


To view the original version on PR Newswire, visit:

SOURCE Cadence Design Systems, Inc.

Cadence Design Systems, Inc.

Review Article Be the first to review this article

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Fall Schedule: A Host of Must-attends
More Editorial  
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
DDR 3-4-5 Developer with VIP for EDA Careers at San Jose, CA
Senior Methodology Automation Engineer for EDA Careers at San Jose, CA
Proposal Support Coordinator for Keystone Aerial Surveys at Philadelphia, PA
Upcoming Events
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
The Rise of Mechatronics at Dassault Systèmes San Diego 5005 Wateridge Vista Drive San Diego CA - Sep 12, 2017
The Rise of Mechatronics at Buca di Beppo - Pasadena 80 West Green Street Pasadena CA - Sep 13, 2017
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy