Kandou Uses Cadence Analog/Mixed-Signal Timing and Power Signoff Tools to Deliver High-Speed SerDes PHY IP Design on 28nm Process

Cadence Mixed-Signal Timing and Power Signoff Solutions Enable Kandou to Achieve First-Pass Silicon 

SAN JOSE, Calif - Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Kandou Bus has fully tested and characterized a 28nm high-speed SerDes PHY IP design named, “Glasswing,” that was implemented using the Cadence® mixed-signal signoff flow. Silicon results confirm that the design can deliver up to 25Gbps per data bus bit, enabling a throughput of 125Gbps over the interface. These specs were achieved while Kandou also reduced dynamic power by 3-5X. 

To meet strict timing and power specifications for this advanced analog/mixed-signal design, Kandou used the OpenAccess-based Cadence Virtuoso® Digital Signoff Timing Solution, which is integrated with the Tempus™ Timing Signoff Solution to provide timing signoff accuracy. In addition, Kandou used the Virtuoso Digital Signoff Power Solution, which is integrated with the Voltus™ IC Power Integrity Solution and the Voltus-Fi Custom Power Integrity Solution to provide power signoff accuracy. The Quantus™ QRC Extraction Solution and the Spectre® Accelerated Parallel Simulator (APS) provided Kandou with a foundry-certified, silicon-accurate, analog/mixed-signal signoff solution. 
Using Cadence’s advanced mixed-signal signoff solution, Kandou achieved timing and power results that correlated within one percent of silicon. The Cadence tools also eliminated the need for further silicon debugging and allowed Kandou to produce a reliable design that yielded a transmission bit error rate (BER) under 1E-15. Kandou was able to achieve their aggressive data throughput goals while reducing power consumption when compared with a traditional, standard DDR3 interface. 
“By using a complete set of Cadence mixed-signal timing and power signoff solutions, we can ensure that our designs are accurate while also increasing our productivity,” said Anant Singh, senior director of engineering at Kandou Bus. “We were able to detect high current spikes and reduce noise levels on the analog and digital blocks, and we also resolved layout issues by analyzing simulation results early in the process. As a result, we were able to deliver a reliable, high-speed SerDes PHY IP design to our customers in far less time than expected.” 
About Cadence 
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at  www.cadence.com.

Email Contact

Review Article Be the first to review this article


Featured Video
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Upcoming Events
SEMICON Europe at Grenoble France - Oct 25 - 27, 2016
ARM TechCon 2016 at Santa Clara Convention Center Santa Clara CA - Oct 25 - 27, 2016
Call For Proposals Now Open! at Santa Clara Convention Center, Santa Clara, CA California CA - Oct 25 - 27, 2016
DeviceWerx - 2016 at Green Valley Ranch Casino & Resort Las Vegas NV - Nov 3 - 4, 2016
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy