First in the Industry to Achieve Over 100 million Program/Erase Cycles at High Temperature with Rewrite Energy of 0.07 mJ/8 KB
TOKYO — (BUSINESS WIRE) — February 3, 2016 — Renesas Electronics Corporation (TSE: 6723), a premier supplier of advanced semiconductor solutions, today announced the development of 90-nanometer (nm) one-transistor MONOS (Note 1) (1T-MONOS) flash memory technology that can be used in combination with a variety of processes, such as CMOS and bipolar CMOS DMOS (BiCDMOS), and provides high program/erase (P/E) endurance and low rewrite energy consumption. Renesas anticipates that the new flash memory circuit technology will enable it to add flash memory to automotive analog devices with improved performance and reliability. This superior circuit technology makes possible the industry’s first P/E endurance of over 100 million cycles under a high junction temperature (Tj) (Note 2) 175°C, while also delivering low rewrite energy of 0.07 mJ/8 KB (millijoule: one thousandth of a joule) for low energy consumption.
Recently, alongside calls for improved fuel efficiency, there is demand for automobiles that offer greater interior space and comfort, which has led to an increase in the number of electronic control units (ECUs) used per vehicle. Along with the issue that automotive control is becoming more and more complicated and the complexity to control them, as result, making ECUs lighter, more power efficient, and more compact have become important issues. In particular, the large number of compact motors used in radiators, water pumps, vehicle air conditioning systems, and the like has created a need for the integration of ECUs and the unification of mechanical and electrical elements (Note 3).
Since it hitherto has not been possible to add flash memory to the automotive analog and power devices that control the high-voltage (HV) drivers used for compact motors without changing the base process used to manufacture them, the need for memory to store tuning data for optimizing the performance of analog circuits is typically addressed either by incorporating eFUSE (Note 4) technology or by utilizing external EEPROM chips. The newly developed flash memory technology restrains additional process costs while providing an easy way to add flash memory to automotive analog and power devices. This means that analog circuits for connecting sensors and motors can employ devices that mix microcontroller (MCU) logic and flash memory based on the new technology. It has the potential to substantially reduce the number of chips used in motor control systems, while helping to make them more compact, lightweight, and power efficient. The new technology will help promote ECU integration and the unification of mechanical and electrical elements and will contribute to the realization of fuel efficient automobiles with more fuel-efficiency, interior space and comfort.
Additionally, the new flash memory technology achieves over 100 million P/E cycles, making it suitable for applications such as automatic calibration or status recording using high-frequency sampling under actual usage conditions in the field. This has the potential to bring greater precision to automotive control and contribute to improved fuel economy.
Key features of the newly developed flash memory technology:
(1) Development of memory architecture combining FN tunneling for P/E operations and high reliability
One-transistor memory cells that allow the mixing of processes with fewer additional mask layers require application of a positive voltage to the memory cell selection gate during read operations. Also, a thinner charge-trapping film is necessary in order to achieve energy-efficient Fowler-Nordheim (FN) tunneling during P/E operations. Both of these are factors that tend to reduce reliability under the high temperature conditions typical of automotive applications. To address this issue, Renesas has combined the one-transistor flash memory technology with the newly-developed array architecture technology that eliminates the need to apply a positive voltage during read operations to prevent reduction reliability under high-temperature conditions and assures the quality essential in automotive products. In addition, the newly developed one-transistor flash memory technology enables reduced power consumption during P/E operations.
(2) Development of technology for weakening electric fields during P/E operations
As the performance of automotive analog devices improves and the trend toward single-chip integration with MCUs continues, and the scope of applications expands from analog circuit tuning to include auto-fitting or data logging functionality, market demand for flash memory with greater P/E endurance is expected to increase. A newly developed adaptable slope pulse control (ASPC) technology enables generation of smoother rewrite pulses as a way to weaken electric fields that can degrade the characteristics of memory cells, boosting P/E endurance to over 100 million cycles.
(3) Development of energy efficient P/E current technology
The newly developed technology uses ASPC when applying rewrite pulses, monitoring the current value when pulses are applied and switching automatically to the optimal clock frequency. This lowers current consumption during P/E operations to a mere 98 μA (microampere: 1 millionth of an ampere), which translates into a rewrite energy of 0.07 mJ/8 KB.
(4) Contribution to reduced power consumption
for eco-friendly automotive systems