Moortec Semiconductor Joins TSMC IP Alliance Program

Moortec Semiconductor, leading supplier of embedded monitoring and optimisation IP, are proud to announce its membership in TSMC’s Hard IP Alliance, a part of TSMC's Open Innovation Platform ®. Alliance membership will allow Moortec to leverage TSMC's advanced technologies with its high performance analog IP and subsystem solutions used for monitoring and controlling conditions on-chip for performance and reliability purposes.

The TSMC IP Alliance Program includes leading IP companies, providing the semiconductor industry's largest catalog of silicon-verified, production-proven and foundry-specific intellectual property (IP). Moortec believes there is a critical need for reliable on-chip monitoring, especially thermal monitoring, for semiconductor geometries of 28-nanometer (nm) and FinFET.

“As transistor geometries shrink and both gate and power densities per unit area increase, designers are seeking ways in which their designs can be optimised dynamically and ways in which device lifetime and reliability can be improved," said Stephen Crosher, Managing Director of Moortec Semiconductor. “We are very excited, as being a member of the Alliance will enable us to collaborate more closely with TSMC which will aid in the design of our compelling IP products and further improve our support to customers.”

“TSMC’s work with Moortec Semiconductor has been very positive for our customers,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division.  “We are pleased to have them participating in our IP Alliance program.”

About Moortec Semiconductor

Moortec Semiconductor, established in 2005, provides high quality analog and mixed-signal Intellectual Property (IP) solutions world-wide for a variety of applications. Having a track record of delivery to tier-1 semiconductor and product companies, Moortec provides a quick and efficient path to market for customer products and innovations. 




Review Article Be the first to review this article
CST: Webinar October 19, 2017

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Field Application Engineer for Teradyne Inc at San Jose, CA
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise